Investigation of breakdown performance in $$L_{g}$$ L g = 20nm novel asymmetric InP HEMTs for future high-speed high-power applications

Investigation of breakdown performance in $$L_{g}$$ L g = 20nm novel asymmetric InP HEMTs... In this paper, we investigated the breakdown performance of novel nanoscale asymmetric InP high-electron-mobility transistors (HEMTs). The novel asymmetric InP HEMT features $$\Gamma $$ Γ -gate, heavily doped multilayer cap, $$n^{+}$$ n + -type In $$_{0.52}$$ 0.52 Ga $$_{0.48}$$ 0.48 As source/drain (S/D) regions, InAs-rich composite channel, SiN passivation and double $$\delta $$ δ -doping planes. The impact of asymmetric gate recess width on DC, RF and breakdown performance of novel asymmetric InP HEMT has been investigated using hydrodynamic carrier transport model along with other physical models such as Shockley–Read–Hall model, recombination models, high-field mobility model and density gradient model. Sentaurus TCAD simulations were carried out at room temperature for gate lengths of 50 and 20 nm in order to analyse the scalability of the new device architecture. In order to consider the quantum effects at nanoscale regime, density gradient model of eQuantum potential was used for TCAD simulations. $$L_{g}$$ L g = 20 nm proposed HEMT achieved a peak $$g_{m}$$ g m and $$I_\mathrm{DS}$$ I DS of 3470 mS/mm and 1300 mA/mm, respectively. The proposed HEMT has a $$f_{T}$$ f T and $$f_\mathrm{max}$$ f max of 749 and 1460 GHz, respectively. The $$L_{g}$$ L g = 20 nm proposed HEMT also showed an ON-state and OFF-state breakdown voltages of 2.2 and 4.5 V, respectively, at a gate recess width of 150 nm. To the best of authors’ knowledge, this is the record combination of DC, RF and breakdown performance reported for InP HEMTs which makes them the most suitable transistors for future high-speed high-power applications. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Journal of Computational Electronics Springer Journals

Investigation of breakdown performance in $$L_{g}$$ L g = 20nm novel asymmetric InP HEMTs for future high-speed high-power applications

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Publisher
Springer Journals
Copyright
Copyright © 2017 by Springer Science+Business Media, LLC
Subject
Engineering; Mathematical and Computational Engineering; Electrical Engineering; Theoretical, Mathematical and Computational Physics; Optical and Electronic Materials; Mechanical Engineering
ISSN
1569-8025
eISSN
1572-8137
D.O.I.
10.1007/s10825-017-1086-4
Publisher site
See Article on Publisher Site

Abstract

In this paper, we investigated the breakdown performance of novel nanoscale asymmetric InP high-electron-mobility transistors (HEMTs). The novel asymmetric InP HEMT features $$\Gamma $$ Γ -gate, heavily doped multilayer cap, $$n^{+}$$ n + -type In $$_{0.52}$$ 0.52 Ga $$_{0.48}$$ 0.48 As source/drain (S/D) regions, InAs-rich composite channel, SiN passivation and double $$\delta $$ δ -doping planes. The impact of asymmetric gate recess width on DC, RF and breakdown performance of novel asymmetric InP HEMT has been investigated using hydrodynamic carrier transport model along with other physical models such as Shockley–Read–Hall model, recombination models, high-field mobility model and density gradient model. Sentaurus TCAD simulations were carried out at room temperature for gate lengths of 50 and 20 nm in order to analyse the scalability of the new device architecture. In order to consider the quantum effects at nanoscale regime, density gradient model of eQuantum potential was used for TCAD simulations. $$L_{g}$$ L g = 20 nm proposed HEMT achieved a peak $$g_{m}$$ g m and $$I_\mathrm{DS}$$ I DS of 3470 mS/mm and 1300 mA/mm, respectively. The proposed HEMT has a $$f_{T}$$ f T and $$f_\mathrm{max}$$ f max of 749 and 1460 GHz, respectively. The $$L_{g}$$ L g = 20 nm proposed HEMT also showed an ON-state and OFF-state breakdown voltages of 2.2 and 4.5 V, respectively, at a gate recess width of 150 nm. To the best of authors’ knowledge, this is the record combination of DC, RF and breakdown performance reported for InP HEMTs which makes them the most suitable transistors for future high-speed high-power applications.

Journal

Journal of Computational ElectronicsSpringer Journals

Published: Oct 6, 2017

References

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