ISSN 1063-7397, Russian Microelectronics, 2006, Vol. 35, No. 2, pp. 94–97. © Pleiades Publishing, Inc., 2006.
Original Russian Text © D.I. Brinkevich, V.S. Prosolovich, S.A. Vabishchevich, A.N. Petlitskii, 2006, published in Mikroelektronika, 2006, Vol. 35, No. 2, pp. 112–116.
Stacking faults are of concern to wafer manufactur-
ers because they adversely affect the performance of
charge-coupled and other semiconductor devices by
increasing leakage in metal–oxide–semiconductor
capacitors, pn junctions, etc. [1, 2]. This experimental
study addresses the inﬂuence of fast-diffusing back-
ground impurities (Fe, Ni, Au, Cu, etc.) on stacking-
fault formation in silicon wafers.
Stacking faults were investigated in Si(111) wafers
of diameter 150 mm made to the KDB-3 speciﬁcation.
The wafers were prepared by annealing in dry oxygen
for 2 h and preferential etching in the Right
etchant for 3 min.
was evaluated by
is the indentation load and
indentation diagonal length, from measurements using
a PMT-3 tester with the indentation load varied over the
range 50–200 g. The hardness tests were performed on
the front wafer side after chemical mechanical polish-
ing. They were accurate to within 2–4%, depending on
item. Microbrittleness was determined by a conven-
tional procedure .
Fast-diffusing background impurities (transition
metals) were introduced into the wafers from a contam-
inated tube of an Oksid-3PO furnace during high-tem-
perature treatment to produce stacking faults.
RESULTS AND DISCUSSION
Stacking faults were detected only within 8 mm
from the wafer edge (Fig. 1a). Their density decreased
from a maximum of
toward the center; the
average size was 2–10
m. In the center, only larger,
needle-shaped defects were observed (Fig. 1b); their
density was below
. The defects were identiﬁed
as vacancy clusters . Such defects reduce chip yield
insigniﬁcantly. Note also that no stacking faults were
detected on control, uncontaminated wafers.
Aside from producing stacking faults, thermal treat-
ment was found to greatly enhance microhardness and
microbrittleness. Statistically, it changed the peripheral
microhardness distribution to the mixture of two nor-
mal distributions (Fig. 2a), whereas that in the center
remained normal, its mean being increased by 10%
(Fig. 2b). It is important to note that the bimodal distri-
bution was found to occur just in the region of stacking
faults as revealed by preferential etching. Also, individ-
ual stacking faults were comparable with indentations
in size (about 10
m). No signiﬁcant correlation was
observed between the standard of wafer-surface prepro-
cessing (chemical or mechanical polishing) and the
properties of stacking faults.
The presence of defects on the periphery was also
evidenced in the pattern of variation of indentation
diagonal length with distance from the wafer edge
(Fig. 3). More speciﬁcally, the spread in diagonal
length was found to decrease from 10–15 to about 4%
in passing from the edge to the center.
The results obtained indicate that fast-diffusing
background impurities (Fe, Au, Ni, Cu, etc.) contribute
to the formation of stacking faults; these (and/or their
nucleation centers) act as drains of the impurities ,
Influence of Background Impurities on the Formation
of Stacking Faults in Silicon Wafers
D. I. Brinkevich*, V. S. Prosolovich*, S. A. Vabishchevich**, and A. N. Petlitskii***
*Belarussian State University, Minsk, Belarus
**Polotsk State University, Novopolotsk, Belarus
***NPO Integral, Minsk, Belarus
Received August 17, 2005
—The microhardness of silicon wafers containing stacking faults is investigated experimentally. The
main ﬁndings are as follows: (1) Fast-diffusing background impurities (Fe, Au, Ni, Cu, etc.) make for the for-
mation of these defects. (2) Stacking faults are manifested in a bimodal statistical distribution of microhardness
made up of two normal distributions. (3) Wafer areas with stacking faults are characterized by higher micro-
MATERIALS AND MICROSTRUCTURE