1063-7397/01/3002- $25.00 © 2001 MAIK “Nauka /Interperiodica”
Russian Microelectronics, Vol. 30, No. 2, 2001, pp. 69–87. Translated from Mikroelektronika, Vol. 30, No. 2, 2001, pp. 5–25.
Original Russian Text Copyright © 2001by Orlikovskii, Rudenko.
The basic trends in the evolution of today’s silicon
IC technology are as follows.
(1) Integration of process steps in clusters, which
combine several modules where a central robot sequen-
tially transfers wafers.
(2) Individual large-diameter wafer processing.
(3) Elimination of operational inspection as a source
of wafer contamination by metal atoms, organic com-
pounds, and dust particles, which reduces production
process monitoring and use of end-point
(5) Replacement of wet processes by vapor-phase
(6) Decrease in substrate temperature owing to the
use of plasma-assisted processes.
(7) Elimination of process correction and manual
control (after process parameters have been set, any
external interference in the process is impermissible);
man-free production (elimination of an operator even
for transporting cassette-packed wafers from installa-
tion to installation).
Leading manufacturers are now passing to process
geometries with 0.13-
m minimum feature sizes on
300-mm wafers. Data from International Technology
Roadmap for Semiconductor, 1999 Edition, show that
the minimum possible feature size provided by optical
lithography tools (about 130 nm) exceeds the minimum
channel length in nanotransistors (85–90 nm in 2002
and 70 nm in 2004). Hence, self-alignment and self-
forming techniques, which loosen requirements for
lithography, need to be used.
It has been shown theoretically and experimentally
that MIS transistors as IC components remain effective
at channel lengths down to 6–10 nm. For a channel
length of 10 nm, the integration density will increase to
gates on a
chip and to a 1-Tbit
DRAM on a
chip with reasonable values
of dissipated power (100–250 W) . However, the
production of ICs with 10-nm channel lengths will not
require lithography tools with like resolution. Flow
routes where self-alignment and self-forming tech-
niques provide 10-nm line widths at a lithographic res-
olution of 35–50 nm have been suggested. Lines as ﬁne
as this can be directly written with a focused electron or
ion beam. However, direct writing is inappropriate for
mass production because of its low throughput. In the
industrial scale, such a resolution can be reached with
projection lithography methods (most likely using soft
X-ray radiation with a wavelength of 13–14 nm) to
As was noted, self-alignment techniques moderate
requirements for lithography processes but impose
more stringent requirements for anisotropic etching of
nanostructures and for conformal deposition of thin
dielectric and conductive ﬁlms. Such an approach is
cost-efﬁcient, since projection exposers are very expen-
sive. Etching and deposition processes must be low-
temperature (without heating wafers) and vapor-phase.
Plasma processes meet all these (and other) require-
ments . They have no alternatives in the context of
the above-mentioned microelectronics trends.
Plasma processes are used or are being developed
Diagnostics of Plasma Processes in Microelectronics:
The Current Status and Immediate Prospects. Part I.
A. A. Orlikovskii and K. V. Rudenko
Institute of Physics and Technology, Russian Academy of Sciences, Nakhimovskii pr. 27a, Moscow, 117218 Russia
Received October 17, 2000
—The necessity of
monitoring plasma processes in present-day microelectronics stems from
the fact that they must provide high precision. New-generation micro- and nanodevices, which will have sharp
interfaces and atomic-level sizes, demand continuous monitoring of process stages. Preference should be given
to built-in monitoring facilities, which exploit highly sensitive physical effects and do not disturb particle ﬂuxes
from a plasma to a substrate. Part I covers advanced diagnostic and monitoring methods, as applied to plasmo-
chemical processes used in microelectronics, with emphasis to optical spectral techniques. They are based on
in-process measuring volume (nonlocal) parameters of a reactive plasma. Processes monitored may include
etching and deposition of semiconductor, metal, and insulating layers, as well as resist stripping and surface