Improving the construction of ORB through FPGA-based acceleration

Improving the construction of ORB through FPGA-based acceleration Binary descriptors have won their place as efficient and effective visual descriptors in several vision tasks. In this context, one of the most widely used binary descriptors to date is the ORB descriptor. ORB is robust against rotation changes, and it uses a learning procedure to generate sampling pairwise tests to construct the descriptor. However, this construction involves a sequential memory access of as many steps as the binary string size. From the latter and motivated by the fact that modern computer vision tasks may require the construction of thousands, if not millions of binary descriptors, we propose to accelerate the construction process of the ORB descriptor via an FPGA-based hardware architecture. The latter is leveraged with a novel arrangement of pairwise tests, which takes advantage of a dual random access memory scheme achieving an acceleration of up to 17 times when compared against the sequential way. The empirical assessment indicates that ORB descriptors obtained from the proposed approach keep a similar performance to that of the original ORB. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Machine Vision and Applications Springer Journals

Improving the construction of ORB through FPGA-based acceleration

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Publisher
Springer Berlin Heidelberg
Copyright
Copyright © 2017 by Springer-Verlag GmbH Germany
Subject
Computer Science; Pattern Recognition; Image Processing and Computer Vision; Communications Engineering, Networks
ISSN
0932-8092
eISSN
1432-1769
D.O.I.
10.1007/s00138-017-0851-5
Publisher site
See Article on Publisher Site

Abstract

Binary descriptors have won their place as efficient and effective visual descriptors in several vision tasks. In this context, one of the most widely used binary descriptors to date is the ORB descriptor. ORB is robust against rotation changes, and it uses a learning procedure to generate sampling pairwise tests to construct the descriptor. However, this construction involves a sequential memory access of as many steps as the binary string size. From the latter and motivated by the fact that modern computer vision tasks may require the construction of thousands, if not millions of binary descriptors, we propose to accelerate the construction process of the ORB descriptor via an FPGA-based hardware architecture. The latter is leveraged with a novel arrangement of pairwise tests, which takes advantage of a dual random access memory scheme achieving an acceleration of up to 17 times when compared against the sequential way. The empirical assessment indicates that ORB descriptors obtained from the proposed approach keep a similar performance to that of the original ORB.

Journal

Machine Vision and ApplicationsSpringer Journals

Published: Jun 24, 2017

References

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