ISSN 1063-7397, Russian Microelectronics, 2016, Vol. 45, No. 7, pp. 532–536. © Pleiades Publishing, Ltd., 2016.
Original Russian Text © N.O. Krylikov, L.A. Morozov, M.L. Plavich, 2015, published in Izvestiya Vysshikh Uchebnykh Zavedenii, Elektronika, 2015, Vol. 20, No. 3, pp. 282–288.
Implementation of Fast High-Order Digital Filters
Based on New-Generation FPGAs
N. O. Krylikov*, L. A. Morozov, and M. L. Plavich
National Research University of Electronic Technology, Moscow, 124498 Russia
Received June 20, 2014
Abstract—Creation of a multichannel block of the 32nd-order bandpass recursive digital filters with a sam-
pling frequency of 48 MHz is considered. Block diagrams of the unit and its component parts are presented.
The detailed description of operation of the unit is given.
Keywords: signals, digital filters, data, FPGA, DAC, ADC
For designing up-to-date electronic devices , in
particular, complex information-computational and
control systems , as a rule field programmable gate
arrays (FPGAs) are applied. Wideband signals,
including pseudo-noise probing signals, which can be
formed by pseudo-random generators, are used in
many radar systems [3, 4].
When the signal reflected from the target is pro-
cessed, it is sufficiently difficult to extract (filter) the
useful component of the signal in the background of
multiple parasitic components, such as a heterodyne
frequency, reflections from local subjects and the
underlying surface, and the harmonics of the pseudo-
random driving signal. In order to obtain acceptable
characteristics of the bandpass filter it is expedient to
use different analog filters at the preliminary filtering
stage and to process the signal by digital methods at
the final stage.
The creation of a multichannel (6 channels) block
of the 32nd-order bandpass recursive digital filters
with a sampling frequency of 48 MHz is considered in
the present work. The input and output data capacity
is 16 bit. To attain the required dynamic range, the
capacity of the filter coefficients should be at least
24 bits. Therefore, the 36-bit intermediate capacity of
the data bus inside each filter is selected.
The posed problem is complicated by the need of
maximally minimizing the volume of the equipment.
According to the preliminary estimate, to construct
the digital filter using a set of unified multipliers, it is
required to use about 300 multipliers with capacities of
36 × 24. From the preliminary simulation results it was
obtained that, when this structure is implemented
based on FPGAs (Xilinx Co.) in the standard built-in
DSP48 block, each theoretical multiplier occupies
four blocks. Thus, the total number of DSP48 blocks
required for fulfilling the posed problem is about 1200.
Of the number of available FPGAs, the most suitable
(including from the viewpoint of the cost) is the
XC7K355T Xilinx microcircuit from the Kintex fam-
ily containing 1440 DSP48 blocks.
OF THE DIGITAL FILTER BLOCK
The block diagram of the digital filter block is
shown in Fig. 1. The basic problem of the unit is the
digital filtering of the data arriving at the ADC of the
preliminary analog filtering channels, the buffering of
filtered data through the FIFO, and their transmission
via the processor interface to the central processor (in
the present work it is not considered) for subsequent
processing. The base of the block is made up of six
independent digital filtering channels, represented in
the block diagram as the 32nd-order filters.
The input signals (external signal group 2) with a
16-bit capacity arrive at the DATA_IN inputs of the
32nd-order filters. The control coefficients for the
32nd-order filters are as follows: 16 coefficients D
(D Coef) with a 24-bit capacity; 16 coefficients B
(B Coef) with a 21-bit capacity; 16 coefficients C
(C Coef) with an 18-bit capacity; 16 shift coefficients
(SHIFT) with a 4-bit capacity; the multiplication fac-
tor NormCoef with an 8-bit capacity; and the decima-
tion factor R with an 8-bit capacity.
All coefficients are common for all six digit-filter-
The output signals of the 32nd-order filters are the
16-bit bus of the FIFO output (FIFO_OUT); the 4-bit