Fully integrated, low drop-out linear voltage regulator in 180 nm CMOS

Fully integrated, low drop-out linear voltage regulator in 180 nm CMOS This paper presents a capacitor-free low dropout (LDO) linear regulator based on a dual loop topology. The regulator utilizes two feedback loops to satisfy the challenges of hearing aid devices, which include fast transient performance and small voltage spikes under rapid load-current changes. The proposed design works without the need of a decoupling capacitor connected at the output and operates with a 0–100 pF capacitive load. The design has been taped out in a $$0.18\,\upmu \hbox {m}$$ 0.18 μ m CMOS process. The proposed regulator has a low component count, area of $$0.012\, \hbox {mm}^2$$ 0.012 mm 2 and is suitable for system-on-chip integration. It regulates the output voltage at 0.9 V from a 1.0–1.4 V supply. The measured results for a current step load from 250 to 500  $$\upmu \hbox {A}$$ μ A with a rise and fall time of $$1.5\,\upmu \hbox {s}$$ 1.5 μ s are an overshoot of 26 mV and undershoot of 26 mV with a settling time of $$3.5\,\upmu \hbox {s}$$ 3.5 μ s when $${C_L}$$ C L between 0 and 100 pF. The proposed LDO regulator consumes a quiescent current of only $$10.5\,\upmu \hbox {A}$$ 10.5 μ A . The design is suitable for application with a current step edge time of 1 ns while maintaining $$\Delta V_{out}$$ Δ V o u t of 64 mV. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Analog Integrated Circuits and Signal Processing Springer Journals

Fully integrated, low drop-out linear voltage regulator in 180 nm CMOS

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Springer US
Copyright © 2017 by Springer Science+Business Media, LLC
Engineering; Circuits and Systems; Electrical Engineering; Signal,Image and Speech Processing
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