Fully depleted SOI CMOS logic gates for low-voltage applications

Fully depleted SOI CMOS logic gates for low-voltage applications Approaches are discussed to the design of low-voltage, low-power VLSI circuits based on SOI nanotransistors. Computer simulations are run to analyze the switching performance of NOT, 2NAND, and 2NOR gates implemented in CMOS technology with fully depleted SOI nanotransistors of different design parameters. The delay and switching power are investigated as functions of supply voltage over a range lying below 1 V, for different values of back-gate bias. The possibility is investigated of operating the transistors of a logic gate in subthreshold mode. This approach is shown to provide a significant reduction in switching power under the right conditions. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

Fully depleted SOI CMOS logic gates for low-voltage applications

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Publisher
Springer Journals
Copyright
Copyright © 2008 by MAIK Nauka
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1134/S1063739708060073
Publisher site
See Article on Publisher Site

Abstract

Approaches are discussed to the design of low-voltage, low-power VLSI circuits based on SOI nanotransistors. Computer simulations are run to analyze the switching performance of NOT, 2NAND, and 2NOR gates implemented in CMOS technology with fully depleted SOI nanotransistors of different design parameters. The delay and switching power are investigated as functions of supply voltage over a range lying below 1 V, for different values of back-gate bias. The possibility is investigated of operating the transistors of a logic gate in subthreshold mode. This approach is shown to provide a significant reduction in switching power under the right conditions.

Journal

Russian MicroelectronicsSpringer Journals

Published: Nov 8, 2008

References

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