Approaches are discussed to the design of low-voltage, low-power VLSI circuits based on SOI nanotransistors. Computer simulations are run to analyze the switching performance of NOT, 2NAND, and 2NOR gates implemented in CMOS technology with fully depleted SOI nanotransistors of different design parameters. The delay and switching power are investigated as functions of supply voltage over a range lying below 1 V, for different values of back-gate bias. The possibility is investigated of operating the transistors of a logic gate in subthreshold mode. This approach is shown to provide a significant reduction in switching power under the right conditions.
Russian Microelectronics – Springer Journals
Published: Nov 8, 2008
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