1063-7397/03/3206- $25.00 © 2003 MAIK “Nauka /Interperiodica”
Russian Microelectronics, Vol. 32, No. 6, 2003, pp. 371–376. Translated from Mikroelektronika, Vol. 32, No. 6, 2003, pp. 459–465.
Original Russian Text Copyright © 2003 by Timoshenkov, Kalugin, Prokopiev.
Microelectronics manufacturing is characterized by
the ongoing increase in circuit complexity and wafer
diameter, accompanied by reduction in minimum fea-
ture size [1, 2]. Figure 1 illustrates the point by showing
how the minimum feature size of memory circuits
decreased with time since the late 1960s.
As a wafer progresses over a sequence of process
steps, some of them may be followed by a chemical
cleaning procedure to prepare the wafer surface for the
step at hand [3, 4]. Chemical processing may also be
applied to a raw wafer, as with wafer bonding in the
fabrication of silicon-on-insulator (SOI) structures .
This paper is concerned with methods for wafer
cleaning in the context of SOI technology.
Any technology of wafer chemical cleaning must
meet the following requirements:
(i) Cleaning must be organized in a sequence of
operations, each designed to remove speciﬁc types of
contaminant; the operations must be compatible with
the other process steps.
(ii) The products of reactions must be easy to
remove from the wafer surface.
Efforts are currently under way to develop advanced
cleaning agents and processes.
Wafer cleaning may involve physical and/or chemi-
cal processes. Cleaning agents may be classiﬁed as wet
or dry. The former category covers vapors as well as
liquids. Aside from chemical processing, wet cleaning
includes rinsing and drying. A dry cleaning agent is a
Evaluation of Si-Wafer Chemical Cleaning Procedures
in Terms of Their Effect on Wafer Topography
S. P. Timoshenkov*, V. V. Kalugin*, and E. P. Prokopiev**
* Moscow Institute of Electronic Engineering (Technical University), Moscow, Russia
** Institute of Theoretical and Experimental Physics, Moscow, Russia
Received January 23, 2003
—The effect of most common chemical cleaning procedures on the topography of Si wafers is studied
experimentally. It is concluded that methods for the inspection of wafer surfaces should be used in conjunction
with each other so as to ensure high accuracy. With sub-1-
m technologies, wafer bonding, etc., one should take
care over reducing surface roughness and selecting wafers and chemicals.
Progress of memory circuits.