Error correction coding for 28-nm CMOS two-phase logic elements

Error correction coding for 28-nm CMOS two-phase logic elements An increase in the upset tolerance of error correction coding using the CMOS two-phase logic elements makes it possible to increase the upset tolerance of encoders/decoders. The results of modeling of the 28-nm CMOS two-phase logic XOR element with various configurations of electric connections in comparison to the single-phase element under the noise effect are presented. A test library of two-phase elements, using which, a route of automated synthesis of irregular topological structures is developed by the example of the Hsiao (72, 64) encoder/decoder. The result is the design of the 28-nm Hsiao encoder/decoder. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

Error correction coding for 28-nm CMOS two-phase logic elements

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Publisher
Pleiades Publishing
Copyright
Copyright © 2015 by Pleiades Publishing, Ltd.
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1134/S1063739715040071
Publisher site
See Article on Publisher Site

Abstract

An increase in the upset tolerance of error correction coding using the CMOS two-phase logic elements makes it possible to increase the upset tolerance of encoders/decoders. The results of modeling of the 28-nm CMOS two-phase logic XOR element with various configurations of electric connections in comparison to the single-phase element under the noise effect are presented. A test library of two-phase elements, using which, a route of automated synthesis of irregular topological structures is developed by the example of the Hsiao (72, 64) encoder/decoder. The result is the design of the 28-nm Hsiao encoder/decoder.

Journal

Russian MicroelectronicsSpringer Journals

Published: Jul 6, 2015

References

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