Enhancement of a-IGZO TFT Device Performance Using a Clean Interface Process via Etch-Stopper Nano-layers

Enhancement of a-IGZO TFT Device Performance Using a Clean Interface Process via Etch-Stopper... To overcome the technological and economic obstacles of amorphous indium-gallium-zinc-oxide (a-IGZO)-based display backplane for industrial production, a clean etch-stopper (CL-ES) process is developed to fabricate a-IGZO- based thin film transistor (TFT) with improved uniformity and reproducibility on 8.5th generation glass substrates (2200 mm × 2500 mm). Compared with a-IGZO-based TFT with back-channel-etched (BCE) structure, a newly formed ES nano-layer (~ 100 nm) and a simultaneous etching of a-IGZO nano-layer (30 nm) and source-drain electrode layer are firstly introduced to a-IGZO-based TFT device with CL-ES structure to improve the uniformity and stability of device for large-area display. The saturation electron mobility of 8.05 cm /V s and the V uniformity th of 0.72 V are realized on the a-IGZO-based TFT device with CL-ES structure. In the negative bias temperature illumination stress and positive bias thermal stress reliability testing under a ± 30 V bias for 3600 s, the measured V th shift of CL-ES-structured device significantly decreased to − 0.51 and + 1.94 V, which are much lower than that of BCE-structured device (− 3.88 V, + 5.58 V). The electrical performance of the a-IGZO-based TFT device with CL-ES structure implies that the economic transfer from a silicon-based TFT process to the metal oxide semiconductor- based process for LCD fabrication is highly feasible. Keywords: Displays, a-IGZO, Thin film transistors, Etch-stopper, Reproducibility, Reliability Background Amorphous indium-gallium-zinc-oxide (a-IGZO) is an Thin film transistor (TFT) backplane with higher excellent metal oxide semiconductor with a high resolution and larger panel size is highly desired in the saturation electron mobility (~ 5–10 cm /V s) and a low flat plane display industry. Semiconductor material with off-current (< 10 pA) [6–10]. The common industrial a high electron mobility is crucial to improve the per- production method for a-Si:H-based TFT backplane is formance of TFT backplane. In particular, a metal oxide five-mask-back-channel-etched (BCE) process. However, semiconductor-based TFT backplane is considered as a a-IGZO nano-film has a very low chemical resistance to promising candidate to overcome the limitation of the typical etchants currently used in the BCE process. silicon-based TFT backplane in terms of mechanical Especially, a-IGZO nano-films would be completely flexibility and electron mobility [1–4]. Although a metal etched in few seconds when they are exposed to Al etch- oxide semiconductor-based TFT backplane shows prom- ant composed of phosphoric acid, nitric acid, and acetic ising properties, the process method with a low-cost acid [11–13]. This uncontrollably fast etching hinders process for both large-scale deposition for industrial the adoption of BCE process for a-IGZO-based TFT application is still needed [5]. backplane. To utilize a-IGZO in BCE-structured back- plane, Cu wiring technology has been developed, as the etchant used in Cu wiring process, which is based on * Correspondence: xyg@uestc.edu.cn H O , is much milder to a-IGZO nano-film than the School of Materials and Energy, University of Electronic Science and 2 2 Technology of China, 2006 Xiyuan Ave, West High-Tech Zone, Chengdu ones used in Al wiring [11, 13]. Unfortunately, a-IGZO 611731, Sichuan, China nano-film is still damaged during Cu wiring process Full list of author information is available at the end of the article © The Author(s). 2018 Open Access This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made. Chung et al. Nanoscale Research Letters (2018) 13:164 Page 2 of 9 even when milder etchant is used. Even milder etchants using CL-ES process deposits gate insulator, IGZO cause damage on the surface of a-IGZO nano-film that nano-layer, and ES nano-layer sequentially, then forms a forms back channel of TFT devices. These damages new ESL mask through dry-etch method. This could cause collapse in the stoichiometric molecular compos- prevent the contamination of a-IGZO nano-layer and ition ratio near the surface of a-IGZO nano-film, leading their interface from etchant, stripper, and solvent. This to the aggravation of uniformity in large-area display newly formed nano-mask helps improve the uniformity and TFT device reliability. To date, conventional six- and stability of TFT device. Compared to conventional mask-etch-stopper (CV-ES) process is developed to BCE-structured device, a-IGZO-based device with CL- fabricate a-IGZO-based TFT backplane with etch- ES structure shows enhanced electrical performances, stopper-layer (ESL) structure [14, 15]. However, this six- namely a higher saturation electron mobility, a high mask ES process may lead to a negative economic opening ratio, and a low power consumption. feasibility. Moreover, this increased number of thin film layers would increase the inter-layer overlap area and re- Methods/Experimental sult in the increased parasitic capacitance and decreased Fabrication of a-IGZO-based TFT Backplane opening ratio [16–18]. Although five-mask ES process The a-IGZO-based TFT backplane with ES structure that produces TFT backplane using half-tone and lift-off fabricated via CL-ES process was as follows (Fig. 1). technology has been reported recently, this process is Firstly, double layer (Mo/Cu:30 nm/250 nm) was used not accessible for the production of a-IGZO-based TFT for gate electrode as it has a reasonably low resistivity. backplane, as their active layer surface is still exposed to Then, gate insulator, silicon nitride (SiNx)/silicon oxide process chemicals such as stripper and photoresist in (SiOx) (300 nm/100 nm), was deposited by plasma- the last step, which may cause considerable contamin- enhanced chemical vapor deposition (PECVD) method. ation to a-IGZO, thus reducing the device quality and This SiNx film is designed to prevent oxidation of Cu the production yield [19–21]. Therefore, the industrial metallizing and diffusion of Cu ion into the gate insula- production method for a-IGZO-based TFT backplane tor. Subsequently, a SiOx thin film was deposited. The with highly uniformity and stability remains challenging. deposition conditions of PECVD SiOx film were 17-KW In this paper, we propose a clean five-mask ES process RF power, 1000 mTorr pressure, 1:55 SiH /N O gas ra- 4 2 (CL-ES) via introducing ESL for fabrication of a-IGZO- tio, and 350 °C temperature. Then, a-IGZO nano-film based TFT backplane. This newly developed CL-ES was deposited to 30 nm using dc rotary magnetron sput- process is highly compatible with the existing process ter. The target had the diameter of 171 mm while the for BCE device. This CL-ES process is designed to have composition was In O :Ga O :ZnO = 1:1:1 mol%. The 2 3 2 3 the equal masks to that of BCE process, which ensures a sputtering parameters for the a-IGZO nano-film were −7 negligible loss of productivity of existing AM-LCD TFT system base pressure of 5~ 9 × 10 Torr, rf sputtering backplane FAB. a-IGZO-based backplane produced power of 10 KW, sputtering pressure of 5-mTorr Ar/O Fig. 1 (Color online) Schematics of a CL-ES, b BCE, and c CV-ES processes Chung et al. Nanoscale Research Letters (2018) 13:164 Page 3 of 9 gas mixture (85% Ar-15% O ). The deposition (TN product standard: five masks) as the BCE temperature is at room condition. Produced a-IGZO process, which is widely used in mass manufacturing. film is annealed at 330 °C for 1 h in clean dry air For comparison, a-IGZO-based TFT backplane with environment. BCE structure was fabricated via BCE process. Secondly, etch-stopper (ES) nano-layer (SiOx) was deposited using PECVD method. ES nano-layer is simul- Characterization taneously deposited to prevent contamination in a- TFT’s I-V measurement was conducted at room IGZO layer. As in BCE process, there is no protective temperature using a semiconductor characteristic layer for a-IGZO nano-film before S/D electrode pat- analyzer. The analyzing condition to evaluate the TFT’s terning process, surface contamination, and damage on stability under negative gate bias temperature illumin- a-IGZO nano-film by S/D etchant when forming TFT ation stress (NBTIS) was as follows. V and V were re- gs ds channel is unavoidable. ES nano-layer in CL-ES process spectively fixed at − 30 and 15 V, and the temperature of can effectively protect TFT channel from external the substrate was kept at 60 °C. The luminance for contamination and damage. The ES nano-layer was de- NBITS was set at 5000 cd/m . The duration of the stress posited to a thickness of 100 nm. The deposition condi- for evaluation continued for 3600 s [23]. Positive gate tions of SiOx thin film were 17-KW RF power, bias thermal stress (PBTS) were tested at a V of 30 V gs 1000mTorr pressure,1:66SiH /N Ogas ratio, and and a V of 15 V, and the substrate temperature was set 4 2 ds 240 °C temperature. The ES nano-mask produced was at 60 °C. The duration of the stress for evaluation etched by dry etching and patterning. During the continued for 3600 s [24]. etching process, CF and O gas were supplied at a 4 2 rate of 2000 sccm/800 sccm. Results and Discussion Thirdly, Mo/Cu/Mo was also used for S/D electrode. a-IGZO-based TFT fabricated via CL-ES process shows To select S/D electrode of a-IGZO TFT, the work func- the same mask number to that of BCE process (Fig. 1). tion difference between metal and a-IGZO was consid- Compared with a-IGZO-based TFT with BCE structure, ered to form an Ohmic contact and the low-resistivity a-IGZO-based TFT with CL-ES structure shows two ad- materials. As described in the etch-stopper process, dur- vantages: (1) a-IGZO-based backplane produced using ing the patterning of ES nano-mask, the a-IGZO nano- CL-ES process deposits gate insulator, a-IGZO nano-layer, films, which are not protected by the etch-stopper layer, and ES nano-layer sequentially, then forms a ESL nano- are already conducted by being bombarded with CF mask through dry-etch method. This newly formed ESL plasma. Therefore, Ohmic contact is formed naturally nano-mask with 100 nm can prevent the exposure of a- with Mo/Cu/Mo [22]. The S/D layers were deposited in IGZO nano-film to etchant, stripper, or photoresist. the thickness of 30 nm/300 nm/30 nm with the same Therefore, the contamination at inter-layer interfaces is ef- sputtering conditions as the gate electrode. In addition, fectively prevented [25]. (2) At the same time, a-IGZO multi-thin film layers of Mo/Cu/Mo and a-IGZO were nano-film is not protected by ES layer but bombarded by batch etched using “H O based Cu etchant containing a CF plasma during the ESL nano-mask formation, thus 2 2 4 fluoride additive” to complete the S/D electrode. The becomes a conductor. This naturally forms the Ohmic 30 nm of Mo added on top of Cu was formed to prevent contact between S/D electrode of following process and a- oxidation of Cu surface by passivation film (SiOx) in the IGZO semiconductor. For another part, a simultaneous next process and to prevent plasma damage of Cu sur- etching of S/D and a-IGZO nano-layer can be one overlay face, during dry etching for passivation hole formation. allowance of ESL-(a-IGZO+S/D metallization) layer, Fourthly, passivation film, divided into two kinds of thin which could decrease the two overlay process error of the film, was deposited using PECVD method. The first pas- a-IGZO-ESL and ES-S/D metallization layer in the con- sivation was made of SiOx thin film. The thin film was ventional ESL process (Fig. 2). The overlay number of the 250 nm thick. The second passivation constituted of SiNx a-IGZO, ES, and S/D layer is reduced, which resulted in thin film. The thickness of the thin film was 200 nm. the decrease in the size of TFT device that lowered the Fifthly, as the pixel electrode, indium tin oxide (ITO) parasitic capacitance. The outcome planar structure is film, which is most commonly used in the display indus- similar to the BCE structure (Fig. 3a, b). try, was utilized. The ITO film was 40 nm thick, and dc Figure 3 shows the SEM images of a-IGZO-based sputtering was used for the deposition. Then, the final TFTs with CL-ES structure (Fig. 3a, c) and BCE struc- annealing was carried out in a clean dry air environment ture (Fig. 3b, d). From the top view, it is difficult to iden- at 230 °C for 1 h using a hot air oven. The electrical tify the differences between CL-ES structure and BCE characteristics of manufactured a-IGZO TFTs were structure (Fig. 3a, b). From the side view, an ES nano- measured using Keysight 4082A Parametric Test System. layer can be found between the a-IGZO nano-layer and This process will obtain the same number of masks the S/D electrode layer in CL-ES structure (Fig. 3c). Chung et al. Nanoscale Research Letters (2018) 13:164 Page 4 of 9 Fig. 2 (Color online) Schematics of simultaneous formation method for TFT channel and S/D electrode in CL-ES process. a The first step that forms gate electrode. b The second step that forms etch-stopper layer. c The third step that forms S/D photo pattern. d The fourth step that forms S/D electrode and active pattern Fig. 3 (Color online) SEM images of a-IGZO TFT (a, b top view; c, d side view) with CL-ES structure (a, c) and BCE structure (b, d) Chung et al. Nanoscale Research Letters (2018) 13:164 Page 5 of 9 Meanwhile, a passivation layer can be found on the top of Table 1 Comparison of I-V characteristics of a-IGZO-based TFT device with CL-ES structure and BCE structure a-IGZO nano-layer in BCE structure (Fig. 3d). In the pre- sented CL-ES process, an a-IGZO nano-layer with a thick- Item Unit CL-ES BCE ness of 30 nm is deposited. Moreover, the damage during V V − 0.85 + 0.50 th_Avg wet etching is negligible. For BCE process, a 70-nm a- V V 0.72 2.14 th_Range IGZO nano-layer is deposited, as a-IGZO layer needs Subthreshold voltage swing V/dec. 0.18 0.77 compensation for etching loss. The difference between the 6 6 I /I ratio – 3.82 × 10 2.62 × 10 on off thicknesses of a-IGZO nano-layers in CL-ES and BCE Mobility cm /V s 8.05 6.03 structures can be observed in the SEM images (Fig. 3c, d). The I-V characteristics of a-IGZO-based TFT with CL- ES structure and BCE structure are compared (Fig. 4). nano-mask. Therefore, the channel length is decided by The saturation electron mobility, threshold voltage, sub- the distance between the a-IGZOs defined at the etch- threshold voltage swing (SS) value, and more characteris- stopper’s sides, but not determined by the distance be- tic values are summarized in Table 1. Notethatthe values tween the electrodes. The channel length of the present summarized in Table 1 are the average number derived CL-ES-structure device is measured to be 10 um. from the center and edge of an 8.5 generation glass sub- As shown in Table 1, the measured values of I /I ra- on off strate. The a-IGZO-based TFT with CL-ES structure real- tio (~ 10 , see Table 1) are approximately 10 times izes V of − 0.8 V, SS value of 0.18 V/dec, and saturation smaller than the typical value (> 10 ) of a-IGZO-based th electron mobility of 8.05 cm /V s. In the a-IGZO-based TFTs. This is because the measuring equipment used TFT with BCE structure, the corresponding results are here is for the 8.5 generation mass production. Long ca- V of + 0.5 V, SS value of 0.77 V/dec, and saturation elec- bles are necessary for these measurements, as the size of th tron mobility of 6.03 cm /V s. Compared to the BCE the industrial equipment is large. The long cables re- structure, CL-ES structure shows an improved device per- sulted in an increased measurement noise. In the follow- formances. However, the on-current characteristic of the ing reliability testing, smaller-scale measuring equipment a-IGZO-based TFT device with CL-ES structure is lower is utilized, and the individual TFT devices is used as spe- than that with BCE-structured device. This is due to the cimen for measurement. In this way, the measured I / on fact that TFT channel structures are different in CL-ES I ratios are all upper 10 (see below). off and BCE structures. Generally, BCE-structured TFT chan- CL-ES process is carefully designed to prevent a-IGZO nel length are the distance between S/D metal electrodes, channel layer being exposed to etchant, photoresist, or and the measured channel length in this study is 5 um stripper. During the process that produces CL-ES [21]. In CL-ES structure, electrodes are in contact with process, gate insulator, a-IGZO nano-layer, and ES the a-IGZO nano-film that is stretched at the side of ESL nano-layer, each inter-layer interface is in contact with Fig. 4 (Color online) Comparison of I-V characteristic of a-IGZO TFTs with CL-ES and BCE structure on the center (a)and edge (b)of 8.5 generation glass substrate Chung et al. Nanoscale Research Letters (2018) 13:164 Page 6 of 9 only DI water for cleaning purpose. Hence, the chemical is 2.14 V (Table 1). In other words, the uniformity of de- contamination is negligible in insulator layer and a- vice performance is significantly improved by CL-ES IGZO nano-layer [25, 26]. However, the BCE process structure. not only exposes channel layer to the chemicals but also Figure 6a, b show the I-V characteristic shift of CL- involves Cu ion diffusion contamination, as the a-IGZO ES-structured device and BCE-structured device ob- channel is directly exposed to Cu metal. This is also tained in NBTIS testing, respectively. The NBTIS testing avoided in device with CL-ES structure. The channel re- results are summarized in Table 2. Under the stress con- gion of the a-IGZO nano-film is well protected by ESL dition described in the Table 2, the V shift of CL-ES- th nano-mask. The low chemical contamination in CL-ES structured device and BCE-structured device are − 0.51 process may lead to a low carrier trap density at the and − 3.88 V, respectively. Additionally, the on-current interface between a-IGZO nano-layer and insulator layer, shift, off-current shift, and SS value variance of the CL- resulting in an excellent SS value. This low chemical ES-structured device are all lower than those of the contamination of a-IGZO-based TFT device via CL-ES BCE-structured device (Table 2); this is because a- process also helps improve the uniformity and reprodu- IGZO-based device with CL-ES-structure can effectively cibility of a-IGZO TFT, which are highly important in prevent the contamination of a-IGZO and lower carrier industrial production [27, 28]. trap density of a-IGZO TFT channel. Especially, when Figure 5 shows the measured I-V characteristic of looking at the result from first 1000 s of stress, no SS TFTs with CL-ES structure and BCE structure derived value change is observed in CL-ES-structured device. from 42 measuring points on an 8.5 generation sub- This phenomenon is comparable to the 0.16 V/dec in- strate. a-IGZO-based TFT with CL-ES structure has a crease in SS value of BCE-structured device, as it shows V range of 0.72 V, while that of BCE-structured device that defect sites, which can form carrier traps on the th Fig. 5 (Color online) a CL-ES structure. b BCE structure’s TFTs I-V transfer characteristic. c 42 measuring points. d the photo of TFT. All measured on an 8.5 generation substrate Chung et al. Nanoscale Research Letters (2018) 13:164 Page 7 of 9 Fig. 6 (Color online) I-V transfer characteristic drift of CL-ES (a, c) and BCE (b, d) TFT obtained from NBITS (a, b) and PBTS testing (c, d) surface of a-IGZO nano-film constituting CL-ES TFT back ion) × 100] of the CL-ES-structured TFT with relatively channel, are not additionally created by electrical and illu- smaller V positive shift (+ 1.94 V) is in the level of 88.2%. th mination stress. These results fully prove that CL-ES- When compared to the BCE-structured TFT's residual ion structured device is much more stable than BCE-structured current ratio of 41.3%, CL-ES-structured TFT is signifi- device. Figure 6c, d show the I-V curve shift of CL-ES- and cantly superior. This shows the important capacity differ- BCE-structured TFTs obtainedfromPBTStesting.The de- ence during designing of gate drive on array (GOA) circuit. tailed PBTS testing results are summarized in Table 3.Both Different from NBTIS, SS value of CL-ES-structured TFT CL-ES-structured TFT and BCE-structured TFT have de- does not have significant variation ((ΔSS 0.06 V/dec), or ra- creased in ion current during PBTS evaluation. This is ther decreases (ΔSS − 0.86) like as BCE-structured TFT. caused by the shift in V to the positive direction. During This is perhaps due to the carriers, accumulate in the inner th PBTS evaluation, residual ion current ratio [(last ion/initial space and interface between gate insulator and a-IGZO Table 2 The on-current shift, off-current shift, and subthreshold voltage swing variance values of CL-ES-structured device and BCE- structured device BL T Bias CL-ES BCE time V bias − 30 V V bias − 30 V g g I (uA) I (pA) V (V) SS (V/dec) I (uA) I (pA) V (V) SS (V/dec) on off th on off th 0nit RT 0 s 7.50 0.01 − 0.71 0.50 8.79 0.21 2.34 1.69 5000nit 60 °C 1000 s 7.92 0.12 − 1.06 0.50 11.83 0.57 0.02 1.85 5000nit 60 °C 3600 s 6.99 0.10 − 1.22 0.83 15.99 6.59 − 1.54 2.11 Shift (1 h–0h) − 0.51 0.09 − 0.51 0.33 7.20 6.38 − 3.88 0.42 Chung et al. Nanoscale Research Letters (2018) 13:164 Page 8 of 9 Table 3 PBTS testing results of CL-ES-structured device and BCE-structured device T Bias CL-ES BCE time V bias + 30 V V bias + 30 V g g I (uA) I (pA) V (V) SS (V/dec) I (uA) I (pA) V (V) SS (V/dec) on off th on off th RT 0 s 8.29 0.10 − 0.32 0.18 10.32 0.14 1.15 1.70 60 °C 1000 s 8.42 0.00 0.14 0.22 5.50 0.20 5.73 0.93 60 °C 3600 s 7.32 0.19 1.62 0.24 4.26 0.07 6.73 0.84 Shift (1 h–0h) − 0.97 0.09 1.94 0.06 − 6.06 − 0.06 5.58 − 0.86 nano-film by positive gate bias, filling the carrier trap site at Acknowledgements The authors appreciate the Chongqing BOE Optoelectronics (CQ1610-PM-IP-001). the early stage, causing decrease in carrier trap Y.X. also acknowledges financial support from the Program for New Century phenomenon. Moreover, the threshold voltage shift Excellent Talents in University (NCET-12-0098). phenomenon occurs by carrier charge trapped near the Funding interface between gate insulator and a-IGZO nano-film. This work is supported by Chongqing BOE Optoelectronics (CQ1610-PM-IP-001). Small threshold voltage shift of CL-ES-structured TFT rep- Y.X. also acknowledges financial support from the Program for New Century resents that the interface and the inner space of a-IGZO Excellent Talents in University (NCET-12-0098). are remarkably clean. In conclusion, PBTS testing also Availability of Data and Materials suggests that CL-ES structure and process lead to a better The authors declare that materials and data are promptly available to readers device reliability. without undue qualifications in material transfer agreements. All data generated or analyzed during this study are included in this article. Conclusions Authors’ Contributions In conclusion, a newly developed CL-ES process has been J-MC and YX conceived and designed the experiments. J-MC, XZ, and FS successfully developed to fabricate a-IGZO-based TFT back- performed the experiments. J-HK, X-LW, SL, and BY analyzed the data. J-HK and XZ wrote the paper. All authors read and approved the final manuscript. plane with five masks for advanced display. The CL-ES process has the advantages of an etch-stopper-layer struc- Competing Interests ture while maintaining the equal number of masks and simi- The authors declare that they have no competing interests. lar device areas to a BCE process, which overcomes the problem of increased mask number and occupied area in Publisher’sNote Springer Nature remains neutral with regard to jurisdictional claims in conventional etch-stopper TFT devices. A newly formed published maps and institutional affiliations. ESL nano-mask and a simultaneous etching of a-IGZO nano-layer and S/D electrode nano-layer enable a high uni- Author details School of Materials and Energy, University of Electronic Science and formity and stability of device for large-area display. In re- Technology of China, 2006 Xiyuan Ave, West High-Tech Zone, Chengdu spect of electrical performance, the reproducibility and 611731, Sichuan, China. Chongqing BOE Optoelectronics Technology CO., reliability of device performance of a-IGZO-based TFT with LTD, Chongqing 400718, China. The 41st Research Institute of CETC, Qingdao 266555, Shandong, China. CL-ES structure are much better than that of BCE- structured device. The a-IGZO-based TFT device has a V th Received: 8 April 2018 Accepted: 8 May 2018 distribution over 42 measuring points TFTs on the 8.5 gen- eration glass substrate of 0.72 V, saturation electron mobility References of 8.05 cm /V s, and SS value of 0.18 V/dec. According to 1. Nakajima Y, Teranishi Y, Kida Y, Maki Y (2006) Ultra-low-power LTPS TFT-LCD reliability evaluation results obtained from NBTIS and technology using a multi-bit pixel memory circuit. J Soc Inf Disp 6:1185–1188 PBTS, V variances before and after stress of CL-ES a- 2. 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Enhancement of a-IGZO TFT Device Performance Using a Clean Interface Process via Etch-Stopper Nano-layers

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Materials Science; Nanotechnology; Nanotechnology and Microengineering; Nanoscale Science and Technology; Nanochemistry; Molecular Medicine
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Abstract

To overcome the technological and economic obstacles of amorphous indium-gallium-zinc-oxide (a-IGZO)-based display backplane for industrial production, a clean etch-stopper (CL-ES) process is developed to fabricate a-IGZO- based thin film transistor (TFT) with improved uniformity and reproducibility on 8.5th generation glass substrates (2200 mm × 2500 mm). Compared with a-IGZO-based TFT with back-channel-etched (BCE) structure, a newly formed ES nano-layer (~ 100 nm) and a simultaneous etching of a-IGZO nano-layer (30 nm) and source-drain electrode layer are firstly introduced to a-IGZO-based TFT device with CL-ES structure to improve the uniformity and stability of device for large-area display. The saturation electron mobility of 8.05 cm /V s and the V uniformity th of 0.72 V are realized on the a-IGZO-based TFT device with CL-ES structure. In the negative bias temperature illumination stress and positive bias thermal stress reliability testing under a ± 30 V bias for 3600 s, the measured V th shift of CL-ES-structured device significantly decreased to − 0.51 and + 1.94 V, which are much lower than that of BCE-structured device (− 3.88 V, + 5.58 V). The electrical performance of the a-IGZO-based TFT device with CL-ES structure implies that the economic transfer from a silicon-based TFT process to the metal oxide semiconductor- based process for LCD fabrication is highly feasible. Keywords: Displays, a-IGZO, Thin film transistors, Etch-stopper, Reproducibility, Reliability Background Amorphous indium-gallium-zinc-oxide (a-IGZO) is an Thin film transistor (TFT) backplane with higher excellent metal oxide semiconductor with a high resolution and larger panel size is highly desired in the saturation electron mobility (~ 5–10 cm /V s) and a low flat plane display industry. Semiconductor material with off-current (< 10 pA) [6–10]. The common industrial a high electron mobility is crucial to improve the per- production method for a-Si:H-based TFT backplane is formance of TFT backplane. In particular, a metal oxide five-mask-back-channel-etched (BCE) process. However, semiconductor-based TFT backplane is considered as a a-IGZO nano-film has a very low chemical resistance to promising candidate to overcome the limitation of the typical etchants currently used in the BCE process. silicon-based TFT backplane in terms of mechanical Especially, a-IGZO nano-films would be completely flexibility and electron mobility [1–4]. Although a metal etched in few seconds when they are exposed to Al etch- oxide semiconductor-based TFT backplane shows prom- ant composed of phosphoric acid, nitric acid, and acetic ising properties, the process method with a low-cost acid [11–13]. This uncontrollably fast etching hinders process for both large-scale deposition for industrial the adoption of BCE process for a-IGZO-based TFT application is still needed [5]. backplane. To utilize a-IGZO in BCE-structured back- plane, Cu wiring technology has been developed, as the etchant used in Cu wiring process, which is based on * Correspondence: xyg@uestc.edu.cn H O , is much milder to a-IGZO nano-film than the School of Materials and Energy, University of Electronic Science and 2 2 Technology of China, 2006 Xiyuan Ave, West High-Tech Zone, Chengdu ones used in Al wiring [11, 13]. Unfortunately, a-IGZO 611731, Sichuan, China nano-film is still damaged during Cu wiring process Full list of author information is available at the end of the article © The Author(s). 2018 Open Access This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made. Chung et al. Nanoscale Research Letters (2018) 13:164 Page 2 of 9 even when milder etchant is used. Even milder etchants using CL-ES process deposits gate insulator, IGZO cause damage on the surface of a-IGZO nano-film that nano-layer, and ES nano-layer sequentially, then forms a forms back channel of TFT devices. These damages new ESL mask through dry-etch method. This could cause collapse in the stoichiometric molecular compos- prevent the contamination of a-IGZO nano-layer and ition ratio near the surface of a-IGZO nano-film, leading their interface from etchant, stripper, and solvent. This to the aggravation of uniformity in large-area display newly formed nano-mask helps improve the uniformity and TFT device reliability. To date, conventional six- and stability of TFT device. Compared to conventional mask-etch-stopper (CV-ES) process is developed to BCE-structured device, a-IGZO-based device with CL- fabricate a-IGZO-based TFT backplane with etch- ES structure shows enhanced electrical performances, stopper-layer (ESL) structure [14, 15]. However, this six- namely a higher saturation electron mobility, a high mask ES process may lead to a negative economic opening ratio, and a low power consumption. feasibility. Moreover, this increased number of thin film layers would increase the inter-layer overlap area and re- Methods/Experimental sult in the increased parasitic capacitance and decreased Fabrication of a-IGZO-based TFT Backplane opening ratio [16–18]. Although five-mask ES process The a-IGZO-based TFT backplane with ES structure that produces TFT backplane using half-tone and lift-off fabricated via CL-ES process was as follows (Fig. 1). technology has been reported recently, this process is Firstly, double layer (Mo/Cu:30 nm/250 nm) was used not accessible for the production of a-IGZO-based TFT for gate electrode as it has a reasonably low resistivity. backplane, as their active layer surface is still exposed to Then, gate insulator, silicon nitride (SiNx)/silicon oxide process chemicals such as stripper and photoresist in (SiOx) (300 nm/100 nm), was deposited by plasma- the last step, which may cause considerable contamin- enhanced chemical vapor deposition (PECVD) method. ation to a-IGZO, thus reducing the device quality and This SiNx film is designed to prevent oxidation of Cu the production yield [19–21]. Therefore, the industrial metallizing and diffusion of Cu ion into the gate insula- production method for a-IGZO-based TFT backplane tor. Subsequently, a SiOx thin film was deposited. The with highly uniformity and stability remains challenging. deposition conditions of PECVD SiOx film were 17-KW In this paper, we propose a clean five-mask ES process RF power, 1000 mTorr pressure, 1:55 SiH /N O gas ra- 4 2 (CL-ES) via introducing ESL for fabrication of a-IGZO- tio, and 350 °C temperature. Then, a-IGZO nano-film based TFT backplane. This newly developed CL-ES was deposited to 30 nm using dc rotary magnetron sput- process is highly compatible with the existing process ter. The target had the diameter of 171 mm while the for BCE device. This CL-ES process is designed to have composition was In O :Ga O :ZnO = 1:1:1 mol%. The 2 3 2 3 the equal masks to that of BCE process, which ensures a sputtering parameters for the a-IGZO nano-film were −7 negligible loss of productivity of existing AM-LCD TFT system base pressure of 5~ 9 × 10 Torr, rf sputtering backplane FAB. a-IGZO-based backplane produced power of 10 KW, sputtering pressure of 5-mTorr Ar/O Fig. 1 (Color online) Schematics of a CL-ES, b BCE, and c CV-ES processes Chung et al. Nanoscale Research Letters (2018) 13:164 Page 3 of 9 gas mixture (85% Ar-15% O ). The deposition (TN product standard: five masks) as the BCE temperature is at room condition. Produced a-IGZO process, which is widely used in mass manufacturing. film is annealed at 330 °C for 1 h in clean dry air For comparison, a-IGZO-based TFT backplane with environment. BCE structure was fabricated via BCE process. Secondly, etch-stopper (ES) nano-layer (SiOx) was deposited using PECVD method. ES nano-layer is simul- Characterization taneously deposited to prevent contamination in a- TFT’s I-V measurement was conducted at room IGZO layer. As in BCE process, there is no protective temperature using a semiconductor characteristic layer for a-IGZO nano-film before S/D electrode pat- analyzer. The analyzing condition to evaluate the TFT’s terning process, surface contamination, and damage on stability under negative gate bias temperature illumin- a-IGZO nano-film by S/D etchant when forming TFT ation stress (NBTIS) was as follows. V and V were re- gs ds channel is unavoidable. ES nano-layer in CL-ES process spectively fixed at − 30 and 15 V, and the temperature of can effectively protect TFT channel from external the substrate was kept at 60 °C. The luminance for contamination and damage. The ES nano-layer was de- NBITS was set at 5000 cd/m . The duration of the stress posited to a thickness of 100 nm. The deposition condi- for evaluation continued for 3600 s [23]. Positive gate tions of SiOx thin film were 17-KW RF power, bias thermal stress (PBTS) were tested at a V of 30 V gs 1000mTorr pressure,1:66SiH /N Ogas ratio, and and a V of 15 V, and the substrate temperature was set 4 2 ds 240 °C temperature. The ES nano-mask produced was at 60 °C. The duration of the stress for evaluation etched by dry etching and patterning. During the continued for 3600 s [24]. etching process, CF and O gas were supplied at a 4 2 rate of 2000 sccm/800 sccm. Results and Discussion Thirdly, Mo/Cu/Mo was also used for S/D electrode. a-IGZO-based TFT fabricated via CL-ES process shows To select S/D electrode of a-IGZO TFT, the work func- the same mask number to that of BCE process (Fig. 1). tion difference between metal and a-IGZO was consid- Compared with a-IGZO-based TFT with BCE structure, ered to form an Ohmic contact and the low-resistivity a-IGZO-based TFT with CL-ES structure shows two ad- materials. As described in the etch-stopper process, dur- vantages: (1) a-IGZO-based backplane produced using ing the patterning of ES nano-mask, the a-IGZO nano- CL-ES process deposits gate insulator, a-IGZO nano-layer, films, which are not protected by the etch-stopper layer, and ES nano-layer sequentially, then forms a ESL nano- are already conducted by being bombarded with CF mask through dry-etch method. This newly formed ESL plasma. Therefore, Ohmic contact is formed naturally nano-mask with 100 nm can prevent the exposure of a- with Mo/Cu/Mo [22]. The S/D layers were deposited in IGZO nano-film to etchant, stripper, or photoresist. the thickness of 30 nm/300 nm/30 nm with the same Therefore, the contamination at inter-layer interfaces is ef- sputtering conditions as the gate electrode. In addition, fectively prevented [25]. (2) At the same time, a-IGZO multi-thin film layers of Mo/Cu/Mo and a-IGZO were nano-film is not protected by ES layer but bombarded by batch etched using “H O based Cu etchant containing a CF plasma during the ESL nano-mask formation, thus 2 2 4 fluoride additive” to complete the S/D electrode. The becomes a conductor. This naturally forms the Ohmic 30 nm of Mo added on top of Cu was formed to prevent contact between S/D electrode of following process and a- oxidation of Cu surface by passivation film (SiOx) in the IGZO semiconductor. For another part, a simultaneous next process and to prevent plasma damage of Cu sur- etching of S/D and a-IGZO nano-layer can be one overlay face, during dry etching for passivation hole formation. allowance of ESL-(a-IGZO+S/D metallization) layer, Fourthly, passivation film, divided into two kinds of thin which could decrease the two overlay process error of the film, was deposited using PECVD method. The first pas- a-IGZO-ESL and ES-S/D metallization layer in the con- sivation was made of SiOx thin film. The thin film was ventional ESL process (Fig. 2). The overlay number of the 250 nm thick. The second passivation constituted of SiNx a-IGZO, ES, and S/D layer is reduced, which resulted in thin film. The thickness of the thin film was 200 nm. the decrease in the size of TFT device that lowered the Fifthly, as the pixel electrode, indium tin oxide (ITO) parasitic capacitance. The outcome planar structure is film, which is most commonly used in the display indus- similar to the BCE structure (Fig. 3a, b). try, was utilized. The ITO film was 40 nm thick, and dc Figure 3 shows the SEM images of a-IGZO-based sputtering was used for the deposition. Then, the final TFTs with CL-ES structure (Fig. 3a, c) and BCE struc- annealing was carried out in a clean dry air environment ture (Fig. 3b, d). From the top view, it is difficult to iden- at 230 °C for 1 h using a hot air oven. The electrical tify the differences between CL-ES structure and BCE characteristics of manufactured a-IGZO TFTs were structure (Fig. 3a, b). From the side view, an ES nano- measured using Keysight 4082A Parametric Test System. layer can be found between the a-IGZO nano-layer and This process will obtain the same number of masks the S/D electrode layer in CL-ES structure (Fig. 3c). Chung et al. Nanoscale Research Letters (2018) 13:164 Page 4 of 9 Fig. 2 (Color online) Schematics of simultaneous formation method for TFT channel and S/D electrode in CL-ES process. a The first step that forms gate electrode. b The second step that forms etch-stopper layer. c The third step that forms S/D photo pattern. d The fourth step that forms S/D electrode and active pattern Fig. 3 (Color online) SEM images of a-IGZO TFT (a, b top view; c, d side view) with CL-ES structure (a, c) and BCE structure (b, d) Chung et al. Nanoscale Research Letters (2018) 13:164 Page 5 of 9 Meanwhile, a passivation layer can be found on the top of Table 1 Comparison of I-V characteristics of a-IGZO-based TFT device with CL-ES structure and BCE structure a-IGZO nano-layer in BCE structure (Fig. 3d). In the pre- sented CL-ES process, an a-IGZO nano-layer with a thick- Item Unit CL-ES BCE ness of 30 nm is deposited. Moreover, the damage during V V − 0.85 + 0.50 th_Avg wet etching is negligible. For BCE process, a 70-nm a- V V 0.72 2.14 th_Range IGZO nano-layer is deposited, as a-IGZO layer needs Subthreshold voltage swing V/dec. 0.18 0.77 compensation for etching loss. The difference between the 6 6 I /I ratio – 3.82 × 10 2.62 × 10 on off thicknesses of a-IGZO nano-layers in CL-ES and BCE Mobility cm /V s 8.05 6.03 structures can be observed in the SEM images (Fig. 3c, d). The I-V characteristics of a-IGZO-based TFT with CL- ES structure and BCE structure are compared (Fig. 4). nano-mask. Therefore, the channel length is decided by The saturation electron mobility, threshold voltage, sub- the distance between the a-IGZOs defined at the etch- threshold voltage swing (SS) value, and more characteris- stopper’s sides, but not determined by the distance be- tic values are summarized in Table 1. Notethatthe values tween the electrodes. The channel length of the present summarized in Table 1 are the average number derived CL-ES-structure device is measured to be 10 um. from the center and edge of an 8.5 generation glass sub- As shown in Table 1, the measured values of I /I ra- on off strate. The a-IGZO-based TFT with CL-ES structure real- tio (~ 10 , see Table 1) are approximately 10 times izes V of − 0.8 V, SS value of 0.18 V/dec, and saturation smaller than the typical value (> 10 ) of a-IGZO-based th electron mobility of 8.05 cm /V s. In the a-IGZO-based TFTs. This is because the measuring equipment used TFT with BCE structure, the corresponding results are here is for the 8.5 generation mass production. Long ca- V of + 0.5 V, SS value of 0.77 V/dec, and saturation elec- bles are necessary for these measurements, as the size of th tron mobility of 6.03 cm /V s. Compared to the BCE the industrial equipment is large. The long cables re- structure, CL-ES structure shows an improved device per- sulted in an increased measurement noise. In the follow- formances. However, the on-current characteristic of the ing reliability testing, smaller-scale measuring equipment a-IGZO-based TFT device with CL-ES structure is lower is utilized, and the individual TFT devices is used as spe- than that with BCE-structured device. This is due to the cimen for measurement. In this way, the measured I / on fact that TFT channel structures are different in CL-ES I ratios are all upper 10 (see below). off and BCE structures. Generally, BCE-structured TFT chan- CL-ES process is carefully designed to prevent a-IGZO nel length are the distance between S/D metal electrodes, channel layer being exposed to etchant, photoresist, or and the measured channel length in this study is 5 um stripper. During the process that produces CL-ES [21]. In CL-ES structure, electrodes are in contact with process, gate insulator, a-IGZO nano-layer, and ES the a-IGZO nano-film that is stretched at the side of ESL nano-layer, each inter-layer interface is in contact with Fig. 4 (Color online) Comparison of I-V characteristic of a-IGZO TFTs with CL-ES and BCE structure on the center (a)and edge (b)of 8.5 generation glass substrate Chung et al. Nanoscale Research Letters (2018) 13:164 Page 6 of 9 only DI water for cleaning purpose. Hence, the chemical is 2.14 V (Table 1). In other words, the uniformity of de- contamination is negligible in insulator layer and a- vice performance is significantly improved by CL-ES IGZO nano-layer [25, 26]. However, the BCE process structure. not only exposes channel layer to the chemicals but also Figure 6a, b show the I-V characteristic shift of CL- involves Cu ion diffusion contamination, as the a-IGZO ES-structured device and BCE-structured device ob- channel is directly exposed to Cu metal. This is also tained in NBTIS testing, respectively. The NBTIS testing avoided in device with CL-ES structure. The channel re- results are summarized in Table 2. Under the stress con- gion of the a-IGZO nano-film is well protected by ESL dition described in the Table 2, the V shift of CL-ES- th nano-mask. The low chemical contamination in CL-ES structured device and BCE-structured device are − 0.51 process may lead to a low carrier trap density at the and − 3.88 V, respectively. Additionally, the on-current interface between a-IGZO nano-layer and insulator layer, shift, off-current shift, and SS value variance of the CL- resulting in an excellent SS value. This low chemical ES-structured device are all lower than those of the contamination of a-IGZO-based TFT device via CL-ES BCE-structured device (Table 2); this is because a- process also helps improve the uniformity and reprodu- IGZO-based device with CL-ES-structure can effectively cibility of a-IGZO TFT, which are highly important in prevent the contamination of a-IGZO and lower carrier industrial production [27, 28]. trap density of a-IGZO TFT channel. Especially, when Figure 5 shows the measured I-V characteristic of looking at the result from first 1000 s of stress, no SS TFTs with CL-ES structure and BCE structure derived value change is observed in CL-ES-structured device. from 42 measuring points on an 8.5 generation sub- This phenomenon is comparable to the 0.16 V/dec in- strate. a-IGZO-based TFT with CL-ES structure has a crease in SS value of BCE-structured device, as it shows V range of 0.72 V, while that of BCE-structured device that defect sites, which can form carrier traps on the th Fig. 5 (Color online) a CL-ES structure. b BCE structure’s TFTs I-V transfer characteristic. c 42 measuring points. d the photo of TFT. All measured on an 8.5 generation substrate Chung et al. Nanoscale Research Letters (2018) 13:164 Page 7 of 9 Fig. 6 (Color online) I-V transfer characteristic drift of CL-ES (a, c) and BCE (b, d) TFT obtained from NBITS (a, b) and PBTS testing (c, d) surface of a-IGZO nano-film constituting CL-ES TFT back ion) × 100] of the CL-ES-structured TFT with relatively channel, are not additionally created by electrical and illu- smaller V positive shift (+ 1.94 V) is in the level of 88.2%. th mination stress. These results fully prove that CL-ES- When compared to the BCE-structured TFT's residual ion structured device is much more stable than BCE-structured current ratio of 41.3%, CL-ES-structured TFT is signifi- device. Figure 6c, d show the I-V curve shift of CL-ES- and cantly superior. This shows the important capacity differ- BCE-structured TFTs obtainedfromPBTStesting.The de- ence during designing of gate drive on array (GOA) circuit. tailed PBTS testing results are summarized in Table 3.Both Different from NBTIS, SS value of CL-ES-structured TFT CL-ES-structured TFT and BCE-structured TFT have de- does not have significant variation ((ΔSS 0.06 V/dec), or ra- creased in ion current during PBTS evaluation. This is ther decreases (ΔSS − 0.86) like as BCE-structured TFT. caused by the shift in V to the positive direction. During This is perhaps due to the carriers, accumulate in the inner th PBTS evaluation, residual ion current ratio [(last ion/initial space and interface between gate insulator and a-IGZO Table 2 The on-current shift, off-current shift, and subthreshold voltage swing variance values of CL-ES-structured device and BCE- structured device BL T Bias CL-ES BCE time V bias − 30 V V bias − 30 V g g I (uA) I (pA) V (V) SS (V/dec) I (uA) I (pA) V (V) SS (V/dec) on off th on off th 0nit RT 0 s 7.50 0.01 − 0.71 0.50 8.79 0.21 2.34 1.69 5000nit 60 °C 1000 s 7.92 0.12 − 1.06 0.50 11.83 0.57 0.02 1.85 5000nit 60 °C 3600 s 6.99 0.10 − 1.22 0.83 15.99 6.59 − 1.54 2.11 Shift (1 h–0h) − 0.51 0.09 − 0.51 0.33 7.20 6.38 − 3.88 0.42 Chung et al. Nanoscale Research Letters (2018) 13:164 Page 8 of 9 Table 3 PBTS testing results of CL-ES-structured device and BCE-structured device T Bias CL-ES BCE time V bias + 30 V V bias + 30 V g g I (uA) I (pA) V (V) SS (V/dec) I (uA) I (pA) V (V) SS (V/dec) on off th on off th RT 0 s 8.29 0.10 − 0.32 0.18 10.32 0.14 1.15 1.70 60 °C 1000 s 8.42 0.00 0.14 0.22 5.50 0.20 5.73 0.93 60 °C 3600 s 7.32 0.19 1.62 0.24 4.26 0.07 6.73 0.84 Shift (1 h–0h) − 0.97 0.09 1.94 0.06 − 6.06 − 0.06 5.58 − 0.86 nano-film by positive gate bias, filling the carrier trap site at Acknowledgements The authors appreciate the Chongqing BOE Optoelectronics (CQ1610-PM-IP-001). the early stage, causing decrease in carrier trap Y.X. also acknowledges financial support from the Program for New Century phenomenon. Moreover, the threshold voltage shift Excellent Talents in University (NCET-12-0098). phenomenon occurs by carrier charge trapped near the Funding interface between gate insulator and a-IGZO nano-film. This work is supported by Chongqing BOE Optoelectronics (CQ1610-PM-IP-001). Small threshold voltage shift of CL-ES-structured TFT rep- Y.X. also acknowledges financial support from the Program for New Century resents that the interface and the inner space of a-IGZO Excellent Talents in University (NCET-12-0098). are remarkably clean. In conclusion, PBTS testing also Availability of Data and Materials suggests that CL-ES structure and process lead to a better The authors declare that materials and data are promptly available to readers device reliability. without undue qualifications in material transfer agreements. All data generated or analyzed during this study are included in this article. Conclusions Authors’ Contributions In conclusion, a newly developed CL-ES process has been J-MC and YX conceived and designed the experiments. J-MC, XZ, and FS successfully developed to fabricate a-IGZO-based TFT back- performed the experiments. J-HK, X-LW, SL, and BY analyzed the data. J-HK and XZ wrote the paper. All authors read and approved the final manuscript. plane with five masks for advanced display. The CL-ES process has the advantages of an etch-stopper-layer struc- Competing Interests ture while maintaining the equal number of masks and simi- The authors declare that they have no competing interests. lar device areas to a BCE process, which overcomes the problem of increased mask number and occupied area in Publisher’sNote Springer Nature remains neutral with regard to jurisdictional claims in conventional etch-stopper TFT devices. A newly formed published maps and institutional affiliations. ESL nano-mask and a simultaneous etching of a-IGZO nano-layer and S/D electrode nano-layer enable a high uni- Author details School of Materials and Energy, University of Electronic Science and formity and stability of device for large-area display. In re- Technology of China, 2006 Xiyuan Ave, West High-Tech Zone, Chengdu spect of electrical performance, the reproducibility and 611731, Sichuan, China. Chongqing BOE Optoelectronics Technology CO., reliability of device performance of a-IGZO-based TFT with LTD, Chongqing 400718, China. The 41st Research Institute of CETC, Qingdao 266555, Shandong, China. CL-ES structure are much better than that of BCE- structured device. The a-IGZO-based TFT device has a V th Received: 8 April 2018 Accepted: 8 May 2018 distribution over 42 measuring points TFTs on the 8.5 gen- eration glass substrate of 0.72 V, saturation electron mobility References of 8.05 cm /V s, and SS value of 0.18 V/dec. According to 1. Nakajima Y, Teranishi Y, Kida Y, Maki Y (2006) Ultra-low-power LTPS TFT-LCD reliability evaluation results obtained from NBTIS and technology using a multi-bit pixel memory circuit. J Soc Inf Disp 6:1185–1188 PBTS, V variances before and after stress of CL-ES a- 2. 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Kamiya T, Nomura K, Hosono H (2009) Origins of high mobility and low Abbreviations operation voltage of amorphous oxide TFTs: electronic structure, electron a-IGZO: Amorphous indium-gallium-zinc-oxide; AM-LCD: Active matrix liquid transport, defects and doping. J Disp Technol 5:273–288 crystal display; BCE: Back channel etch; ESL: Etch-stopper layer; GOA: Gate 7. Kamiya T, Nomura K, Hosono H (2010) Present status of amorphous drive on array; NBTIS: Negative bias temperature illumination stress; In–Ga–Zn–O thin-film transistors. Sci Technol Adv Mater 11:044305 PBTS: Positive bias temperature stress; SiNx: Silicon nitride; SiOx: Silicon 8. Kamiya T, Nomura K, Hosono H (2009) Electronic structure of the oxide; SS: Subthreshold swing; TFT: Thin film transistor; TN LCD: Twisted amorphous oxide semiconductor a-InGaZnO4–x: Tauc–Lorentz optical nematic liquid crystal display model and origins of subgap states. Phys Status Solidi 206:860–867 Chung et al. Nanoscale Research Letters (2018) 13:164 Page 9 of 9 9. Nomura K, Kamiya T, Ohta H, Shimizu K, Hirano M, Hosono H (2008) Relationship between non-localized tail states and carrier transport in amorphous oxide semiconductor, In–Ga–Zn–O. Phys. Status Solidi 205: 1910–1914 10. Kamiya T, Nomura K, Hosono H (2011) Subgap states, doping and defect formation energies in amorphous oxide semiconductor a-InGaZnO4 studied by density functional theory. Phys Status Solidi 207:1698–1703 11. Ryu SH, Park YC, Mativenga M, Kang DH, Jang J (2012) Amorphous-InGaZnO4 thin-film transistors with damage-free back channel wet-etch process. ECS Solid State Lett 1:17–19 12. Um JG, Mativenga M, Geng D, Li X, Jang J (2014) High speed a-A-IGZO TFT-based gate driver by using back channel etched structure. Sid Symp Dig Tech Pap. 45:968–971 13. Park YC, Um JG, Mativenga M, Jang J (2015) Modification of electrode-etchant for sidewall profile control and reduced back-channel corrosion of inverted- staggered metal-oxide TFTs. ECS J Solid State Sci Technol. 4:124–129 14. Kim M, Jeong JH, Lee HJ, Ahn TK, Shin HS, Park JS, Jeong JK, Mo YG, Kim HD (2007) High mobility bottom gate InGaZnO thin film transistors with SiOx etch stopper. Appl Phys Lett 90:212114–212114 15. Tsormpatzoglou A, Hastas NA, Khan S, Hatalis M, Dimitriadis CA (2012) Comparative study of active-over-metal and metalover-active amorphous A-IGZO thin-film transistors with low-frequency noise measurements. IEEE Electron Device Lett. 33:555–557 16. Kim B, Ryoo CI, Kim SJ, Bae JU, Seo HS, Kim CD, Han MK (2011) New depletion-mode A-IGZO TFT shift register. IEEE Electron Device Lett. 32:1092–1094 17. Lin CL, Chang WY, Hung CC (2013) Compensating pixel circuit driving AMOLED display with a-A-IGZO TFTs. IEEE Electron Device Lett 34:1166–1168 18. Kim B, Choi SC, Lee SY, Kuk SH, Jang YH, Kim CD, Han MK (2011) A depletion-mode a-A-IGZO TFT shift register with a single low-voltage-level power signal. IEEE Electron Device Lett. 32:1092–1094 19. Yang J, Jung S, Woo C, Lee J, Jun M, Kang I (2015) A novel 5-mask etch- stopper pixel structure with a short channel oxide semiconductor TFT. Sid Symp Dig Tech Pap 46:304–307 20. Yang JY, Jung SH, Woo CS, Lee JH, Park JH, Jun MC (2014) A short-channel TFT of amorphous In–Ga–Zn–O semiconductor pixel structure with advanced five-mask process. IEEE Electron Device Lett. 35:1043–1045 21. Chen JH, Huang TH, Lu IM, Chen PF, Chen DI (2000) Study of 5-mask TFT array process with low cost, high yield and high performance characteristics. Proc SPIE 4079:210–216 22. Um JK, Lee SH, Jin SH, Mativenga M, Oh SY, Lee CH, Jang J (2015) High-performance homojunction a-IGZO TFTs with selectively defined low-resistive a-IGZO source/drain electrodes (2015). IEEE Trans. Electron Devices 62:2212–2218 23. Um JG, Mativenga M, Migliorato P, Jang J (2012) Increase of interface and bulk density of states in amorphous-indium-gallium-zinc oxide thin-film transistors with negative-bias-under-illumination-stress time. Appl Phys Lett 101:468–1426 24. Chowdhury MDH, Migliorato P, Jang J (2011) Time temperature dependence of positive gate bias stress and recovery in amorphous indium-gallium-zinc- oxide thin-film-transistors. Appl Phys Lett 98:044305 25. Mativenga M, Um JK, Kang DH, Mruthyunjaya RK, Chang JH, Heiler GN, Tredwell TJ, Jang J (2012) Edge effects in bottom-gate inverted staggered thin-film transistors. IEEE Trans Electron Devices 59:2501–2506 26. Kumomi H, Yaginuma S, Omura H, Goyal A, Sato A, Watanabe M, Shimada M, Kaji N, Takahashi K, Ofuji M, Watanabe T, Itagaki N, Shimizu H, Abe K, Tateishi Y, Yabuta H, Iwasaki T, Hayashi R, Aiba T, Sano M (2009) Materials, devices, and circuits of transparent amorphous-oxide semiconductor. J Disp Technol 5:531–540 27. Chowdhury MDH, Um JG, Jang J (2014) Remarkable changes in interface O vacancy and metal-oxide bonds in amorphous indium-gallium-zinc-oxide thin-film transistors by long time annealing at 250°C. Appl Phys Lett 105:2945 28. Ochi M, Morita S, Takanashi Y, Tao H (2015) Electrical characterization of BCE-TFTs with a-IGZTO oxide semiconductor compatible with Cu and Al interconnections. Sid Symp Dig Tech Pap. 46:853–856

Journal

Nanoscale Research LettersSpringer Journals

Published: May 29, 2018

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