Effect of barrier-layer deposition conditions on reliability of on-chip wiring

Effect of barrier-layer deposition conditions on reliability of on-chip wiring An experimental investigation is carried out to evaluate the reliability of on-chip aluminum wiring in relation to the conditions of barrier-layer deposition, with the barrier material being polycrystalline or amorphous silicon produced by pyrolyzing silane. The highest values of electromigration activation energy in the conductor are achieved with hydrogenated amorphous silicon, deposited at a suitably reduced temperature. For wiring patterns lying on a complex topography, the influence of steps on the electrical performance of wires is found to be the main factor in wiring reliability. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

Effect of barrier-layer deposition conditions on reliability of on-chip wiring

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Publisher
SP MAIK Nauka/Interperiodica
Copyright
Copyright © 2011 by Pleiades Publishing, Ltd.
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1134/S1063739711040056
Publisher site
See Article on Publisher Site

Abstract

An experimental investigation is carried out to evaluate the reliability of on-chip aluminum wiring in relation to the conditions of barrier-layer deposition, with the barrier material being polycrystalline or amorphous silicon produced by pyrolyzing silane. The highest values of electromigration activation energy in the conductor are achieved with hydrogenated amorphous silicon, deposited at a suitably reduced temperature. For wiring patterns lying on a complex topography, the influence of steps on the electrical performance of wires is found to be the main factor in wiring reliability.

Journal

Russian MicroelectronicsSpringer Journals

Published: Sep 30, 2011

References

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