ISSN 1063-7397, Russian Microelectronics, 2006, Vol. 35, No. 3, pp. 162–176. © Pleiades Publishing, Inc., 2006.
Original Russian Text © A.V. Kirgizova, A.Y. Nikiforov, N.G. Grigor’ev, I.V. Poljakov, P.K. Skorobogatov, 2006, published in Mikroelektronika, 2006, Vol. 35, No. 3, pp. 191–208.
In Russia, random-access-memory (RAM) very-
large-scale-integration (VLSI) circuits of highest
immunity to transient-radiation upset are commonly
implemented in silicon-on-sapphire (SOS) technology,
and plans are under way for introducing other silicon-
Transient-radiation upsets in SOS complementary
metal–oxide–semiconductor (CMOS) memory have
been the subject of analysis and simulation for almost
20 years [1–8]. As a result, the 1620 series of SOS
memory circuits was developed, offering an upset
immunity as high as 10
, together with SPICE upset
models for particular elements.
On the other hand, we do not fully understand the
dominant mechanisms of transient-radiation upset in
CMOS memory circuits made in SOS technology, nor
do we know for certain how to improve the upset immu-
nity of such circuits. These issues are addressed below.
2. SOS-RAM PRINCIPLES AND STRUCTURE
Figure 1 shows schematically the general organiza-
tion of a RAM circuit realized in SOS technology. The
memory is constructed as a rectangular array of mem-
ory cells forming rows and columns. It also includes a
row decoder, a column decoder, a control unit (it gener-
ates read, write, etc., signals), a sense ampliﬁer, and a
buffer to provide an interface between the memory and
external circuitry. An SOS memory circuit constitutes
static RAM with a well-known timing diagram.
Figure 2 depicts a conventional, six-transistor
CMOS memory cell. Data is stored as the difference
of the voltages
at the respective inputs of two
inverters forming a ﬂip-ﬂop; alternatively, the output
inverter voltages may be used. When exposed to tran-
sient ionizing radiation, all the materials of a memory
circuit (silicon, sapphire, silicon dioxide, and package
ceramics) will become ionized and conduct photocur-
rent pulses at least as long as the radiation pulse; the
photocurrent pulse height depends on the electrode
geometry, the interelectrode potential difference, the
geometry and properties of the materials exposed, and
the dose rate.
Calculations and measurements have shown that a
response to transient ionizing radiation can be repre-
sented by a source of a current pulse connected in par-
allel with each transistor in whatever state; the current
pulse height can be comparable with the on-state drain
current [1–8]. As a result,
approach levels close to half the supply voltage
this process should be intensiﬁed by both transistor
state reversals and the positive feedback. The reduction
can also be inﬂuenced by radiation-induced dis-
turbances to the respective voltages at bit lines 1 and 2,
which must be zero (or equal to
) in the store mode.
The disturbances are associated with photocurrents
ﬂowing through the switch transistors in the off state.
This effect will be especially strong if most of the mem-
ory cells in a column contain the same data.
The voltage to switch a ﬂip-ﬂop depends on the
spread in its parameters associated with technological
factors. Therefore, if
is reduced to below the switch-
ing threshold, the postirradiation state of the ﬂip-ﬂop
may differ from that immediately before the irradiation,
in which case an upset is said to occur.
To maximize upset immunity, the respective chan-
nel widths of p- and n-channel transistors should be
selected such that the respective channel currents will
Dominant Mechanisms of Transient-Radiation
Upset in CMOS RAM VLSI Circuits Realized in SOS Technology
A. V. Kirgizova, A. Y. Nikiforov, N. G. Grigor’ev, I. V. Poljakov, and P. K. Skorobogatov
Specialized Electronic Systems (SPELS), Moscow, Russia
Received December 20, 2005
—The dominant mechanisms are analyzed of transient-radiation upset in CMOS RAM VLSI circuits
realized in SOS technology. Data reliability under transient irradiation is discussed in relation to photocurrents,
rail-span collapse, and the circuit and layout design of memory cells. The response is simulated of SOS inte-
grated resistors to transient radiation. Optimal parameter values are thus determined for the resistor used in the
RC network of a memory cell. It is found that the data reliability of the memory circuits considered is affected
by the cross coupling of memory cells sharing a read/write line. The lifetime of radiation-induced charge car-
riers is estimated by experiment and computer simulation.
AND SIMULATION IN SILICON MICROELECTRONICS