1063-7397/05/3406- © 2005 MAIK “Nauka /Interperiodica”
Russian Microelectronics, Vol. 34, No. 6, 2005, pp. 386–396. Translated from Mikroelektronika, Vol. 34, No. 6, 2005, pp. 455–465.
Original Russian Text Copyright © 2005 by Kroupkina.
The advantages and potential applications of sili-
con-on-sapphire (SOS) and silicon-on-insulator (SOI)
structures become more fully understood as the manu-
facturing technology is reﬁned. SOS and SOI metal–
oxide–semiconductor ﬁeld-effect transistors (MOS-
FETs) are notable for their high drain currents, low
source and drain capacitances, radiation hardness, and
immunity to latchup. They allow one to build high-
speed, low-power integrated circuits (ICs) very suited
to microprocessor, dynamic-memory, analog, and
microwave applications [1–3].
SOS and SOI MOSFETs differ from their bulk
counterparts in some important respects. The back sili-
con–insulator interface and the back gate have an inﬂu-
ence on the current through the gate region, which can
lead to the formation of a back channel . Insulation
of the gate region results in ﬂoating-body effects :
the kink effect due to drain avalanche multiplication,
threshold-voltage reduction induced by a positive body
bias, and current variation under switching.
The devices may operate at full or partial depletion
of the Si ﬁlm, depending on the thickness and doping
level of the ﬁlm. Full-depletion performance is
adversely affected by high source and drain resistances
and the across-the-wafer variation of ﬁlm thickness .
The performance of partially depleted devices in terms
of parameter reproducibility, hysteresis, and break-
down voltage is improved by creating a contact to the
ﬂoating region under the gate in order to prevent charge
accumulation and potential deviation. This also
enhances radiation hardness. Such a contact is provided
in devices of suitable structure  or geometry .
Figure 1 represents main geometries of SOI MOS-
FETs. Except for the I type, each geometry has a con-
tact region, the body, to the gate region. In the A-type
device the source region has
portions adjacent to the
channel. For any geometry, device simulation has to be
run in all three dimensions.
GOALS OF DEVICE AND PROCESS
Any software tool for device and process simulation
addresses three different aspects of the task in an inte-
grated way; these are process simulation, computation
of device electrical characteristics, and circuit-parame-
ter extraction. Such a simulator is seen as a virtual fac-
tory, also known as a virtual fab , since it can repre-
sent process steps and measurement procedures in a far
shorter amount of time and at a much lower cost as
compared with the actual fabrication process.
As the industry changes to progressively smaller
feature sizes, device and process simulation plays an
increasingly important role in device and process
design. The main reasons are growing production
costs and the fact that conventional structural-char-
acterization techniques such as secondary-ion mass
spectroscopy are less accurate on the nanometer
Device and process simulation can provide reliable
information on the relationship between process
parameters and electrical characteristics. The reliability
is ensured by developing models that are functional,
accurate, physically valid, and easy to use to a greater
extent, provided that the models are regularly adjusted
to the results of practical experiments.
As noted above, the three-dimensional (3D) nature
of advanced thin-ﬁlm device structures makes simula-
tion very difﬁcult. Yet simulation is the only way to
extract the complete set of circuit parameters in some
An example is the A-type MOSFET in Fig. 1d.
Notice that the contact is common to the
the rest of the source, so that the source and the body
are always at the same potential. It is therefore impos-
characteristics at different body biases
from which to extract circuit parameters.
Device and Process Simulation of SOS and SOI MOSFETs
T. Yu. Kroupkina
Moscow Institute of Electronic Engineering (Technical University), Moscow, Russia
Received February 4, 2005
—The 3D modeling of thin-ﬁlm structures used in SOS and SOI MOSFETs with different geometries
is discussed. For such devices a computer simulation of electrical performance is run with the ISE TCAD sim-
ulator. A comparison with experimental results is made. Ways to increase the accuracy of the underlying model