Determination of the delay of a programmable logic array

Determination of the delay of a programmable logic array A modification of the programmable logic array (PLA), whose operation is controlled by a clock signal, is suggested. The problem of determination of the time delay of such PLA is treated. The time delay is determined by simulating the circuit-design description of the PLA represented as a network of constituent transistors. The circuit-design description is generated on the basis of the logic description of a set of Boolean functions implemented with the PLA. To reduce the time of simulation, the method of minimization of the number of test vectors is suggested. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

Determination of the delay of a programmable logic array

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Publisher
Springer Journals
Copyright
Copyright © 2010 by Pleiades Publishing, Ltd.
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1134/S1063739710040074
Publisher site
See Article on Publisher Site

Abstract

A modification of the programmable logic array (PLA), whose operation is controlled by a clock signal, is suggested. The problem of determination of the time delay of such PLA is treated. The time delay is determined by simulating the circuit-design description of the PLA represented as a network of constituent transistors. The circuit-design description is generated on the basis of the logic description of a set of Boolean functions implemented with the PLA. To reduce the time of simulation, the method of minimization of the number of test vectors is suggested.

Journal

Russian MicroelectronicsSpringer Journals

Published: Jul 21, 2010

References

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