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V.N. Yarmolik (1988)
Kontrol’ i diagnostika tsifrovykh uzlov EVM
G. Umanesan, E. Fujiwara (2003)
A Class of Random Multiple Bits in a Byte Error Correcting and Single Byte Error Detecting (S_t/b EC-S_bED) CodesIEEE Trans. Computers, 52
Xiaoling Sun, M. Serra (1992)
MERGING CONCURRENT CHECKING AND OFF-LINE BISTProceedings International Test Conference 1992
R.A. Frohwerk (1977)
Signature Analysis: A New Digital Field Service MethodHewlett-Packard J., 28
X. Sun, M. Serra (1992)
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
S. Hellebrand, H. Wunderlich, A. Ivaniuk, Y. Klimets, V. Yarmolik (2002)
Efficient Online and Offline Testing of Embedded DRAMsIEEE Trans. Computers, 51
S. Hellebrand, H. Wunderlich, A. Ivaniuk, Y. Klimets, V. Yarmolik (1999)
Error detecting refreshment for embedded DRAMsProceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)
I. Otung (2004)
Error Control CodingIEEE Trans. Inf. Theory, 51
F. MacWilliams, N. Sloane (1977)
The Theory of Error-Correcting Codes
G. Neuberger, F. Kastensmidt, L. Carro, R. Reis (2003)
A multiple bit upset tolerant SRAM memoryACM Trans. Design Autom. Electr. Syst., 8
F. Alzahrani, T. Chen (1994)
ICCS’94: Proceedings of the 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
V. Yarmolik, S. Hellebrand, H. Wunderlich (1998)
Self-adjusting output data compression: An efficient BIST technique for RAMsProceedings Design, Automation and Test in Europe
Fahad Alzahrani, Tom Chen (1994)
On-chip TEC-QED ECC for ultra-large, single-chip memory systemsProceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors
G. Umanesan, E. Fujiwara (2003)
A Class of Random Multiple Bits in a Byte Error Correcting (S T/B EC) Codes for Semiconductor Memory SystemIEEE Trans. Comput., 52
V.N. Yarmolik, I.A. Murashko, A. Kummert, A. A. Ivaniuk (2005)
Nerazrushayushchee testirovanie zapominayushchikh ustroistv
A new version of Self-Adjusting Output Data Compression is put forward as a method of multiple-error detection in RAM. The parity-check matrix of a linear code with suitably large code distance is used to compress RAM content. The matrix columns are essentially generated in real time from memory addresses. The reliability of the method is determined by the code distance of the parity-check matrix used for compression. A hardware realization of the method is proposed.
Russian Microelectronics – Springer Journals
Published: Jul 24, 2007
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