ISSN 1063-7397, Russian Microelectronics, 2007, Vol. 36, No. 2, pp. 127–134. © Pleiades Publishing, Ltd., 2007.
Original Russian Text © V.D. Baikov, A.A. Garmash, Yu.B. Rogatkin, A.N. Sevryukovv, 2007, published in Mikroelektronika, 2007, Vol. 36, No. 2, pp. 148–156.
Frequency synthesis represents the key aspect of
clocking in modern high-speed microprocessors. When
realized as a phase-locked loop (PLL), frequency syn-
thesizers display high precision and allow simple
implementation of programmable frequency switching.
Even with the diverse requirements to be satisﬁed, it is
possible to design clock PLLs from tried and tested
building blocks by means of suitable software. This
approach results in a high standard of design as well as
shortening the turnaround time. It is employed in the
ﬁeld of system-on-a-chip technology.
Baikov et al.  presented a building-block method-
ology for the circuit and layout computer-aided design
of PLL frequency synthesizers to be operated at 1–
1500 MHz. It allows one to use well-known PLL com-
BASIC PLL FREQUENCY SYNTHESIZER:
STRUCTURE AND OPERATING PRINCIPLE
The structure of the basic PLL frequency synthe-
sizer is shown in Fig. 1. It essentially contains a nega-
tive-feedback loop that ensures the relation
is the frequency of the voltage-controlled
is the reference frequency, and
is usually determined by an
off-chip piezoelectric crystal.
An output frequency is synthesized by division of
the VCO frequency. This is performed by the synthe-
sizer’s digital section, which consists of the program-
mable frequency dividers.
The analog section is made up of the following
(i) stabilized bias unit,
(ii) phase–frequency detector (PFD),
(iii) charge pump (CP),
(iv) loop ﬁlter,
The loop ﬁlter is implemented as a second-order
low-pass ﬁlter comprising the integrating capacitor
The main performance parameters of a PLL fre-
quency synthesizer are as follows:
(i) frequency range and step size,
(ii) reference frequency,
(iii) phase noise and jitter,
(iv) lock time,
(v) output waveform,
(vi) VCO parameters,
(vii) power consumption.
The phase noise and jitter are used to compare a syn-
thesized signal against the reference one. The output
waveform is most often a square waveform.
Mathematically, the PLL is described in the
domain by the normalized step response
Design of Fully Integrated Programmable PLL Frequency
Synthesizers for Microprocessor Clocking at 1–1500 MHz
V. D. Baikov, A. A. Garmash, Yu. B. Rogatkin, and A. N. Sevryukov
Moscow Engineering Physics Institute (State University), Moscow, Russia
ZAO Angstrem-SBIS, Russia
Received February 7, 2006
—This paper is concerned with the design of fully integrated programmable PLL frequency synthe-
sizers for microprocessor clocking at 1–1500 MHz. The focus is on the circuit conﬁguration and performance
parameters of the basic analog units of the PLL: the stabilized bias unit, phase–frequency detector, charge
pump, loop ﬁlter, and voltage-controlled oscillator (VCO). The data examined are obtained by measurements
on ICs fabricated by a 0.25- or 0.18-
m established CMOS technology. The circuit conﬁgurations are presented
of VCOs that are tunable up to 1–1.3 GHz or up to over 2 GHz; they are designed to be implemented in a 0.25-
m technology, respectively. Also addressed is the design of the digital section of PLL synthesizers with
a tuning range extending from 1 to over 1000 MHz. The PLL frequency and step responses, current consump-
tion, and jitter performance are presented and investigated.
PACS numbers: 85.40.BL