Design and theoretical comparison of input ESD devices in 180 nm CMOS with focus on low capacitance

Design and theoretical comparison of input ESD devices in 180 nm CMOS with focus on low capacitance With the last decade’s advances in sensor technologies and packaging techniques, there are several applications where the input capacitance and the leakage current of the integrated circuit (IC) front-end limit the readout accuracy of sensor systems. In particular, optimization of the electrostatic discharge (ESD) protection devices at the IC input could improve performance. Specifically, such optimization should involve reduction of parasitic capacitance and leakage current while maintaining the ESD robustness. Several ESD devices have been analyzed against input capacitance, leakage current and robust ESD performance. The first device of interest is a diode, as the simplest solution and then there are three MOS transistor based devices, gate-grounded NMOS (GGNMOS), gate-coupled NMOS (GCNMOS), and substrate pump NMOS (SPNMOS). The target fabrication process is 180 nm CMOS. Theoretical analysis of capacitance simulated with Cadence® in 180 nm CMOS design kit including layout extracted parasitics in combination with TCAD Sentaurus® simulations of current density and temperature is presented for selected ESD devices. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png e & i Elektrotechnik und Informationstechnik Springer Journals

Design and theoretical comparison of input ESD devices in 180 nm CMOS with focus on low capacitance

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Publisher
Springer Journals
Copyright
Copyright © 2018 by The Author(s)
Subject
Engineering; Electrical Engineering; Computer Hardware; Software Engineering/Programming and Operating Systems
ISSN
0932-383X
eISSN
1613-7620
D.O.I.
10.1007/s00502-017-0569-0
Publisher site
See Article on Publisher Site

Abstract

With the last decade’s advances in sensor technologies and packaging techniques, there are several applications where the input capacitance and the leakage current of the integrated circuit (IC) front-end limit the readout accuracy of sensor systems. In particular, optimization of the electrostatic discharge (ESD) protection devices at the IC input could improve performance. Specifically, such optimization should involve reduction of parasitic capacitance and leakage current while maintaining the ESD robustness. Several ESD devices have been analyzed against input capacitance, leakage current and robust ESD performance. The first device of interest is a diode, as the simplest solution and then there are three MOS transistor based devices, gate-grounded NMOS (GGNMOS), gate-coupled NMOS (GCNMOS), and substrate pump NMOS (SPNMOS). The target fabrication process is 180 nm CMOS. Theoretical analysis of capacitance simulated with Cadence® in 180 nm CMOS design kit including layout extracted parasitics in combination with TCAD Sentaurus® simulations of current density and temperature is presented for selected ESD devices.

Journal

e & i Elektrotechnik und InformationstechnikSpringer Journals

Published: Jan 10, 2018

References

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