Design and Analysis of Low Noise Optimization Amplifier Using Reconfigurable Slotted Patch Antenna

Design and Analysis of Low Noise Optimization Amplifier Using Reconfigurable Slotted Patch Antenna This paper approaches a novel design theory of Low noise amplifier using reconfigurable rectangular shaped slotted patch antenna for 10.3–14 GHz receiver applications. In this approach, a Berkeley short-channel4 metal oxide field effect transistor (BSIM4, MOSFET) device is loaded in rectangular slotted patch antenna which results in wide band frequency of operation. To understand the design and analysis of low noise amplifier, an equivalent circuit model is extracted from the rectangular slotted patch antenna using finite element method (FEM) simulator where the slotted effect is considered. An extraction of equivalent model from the slotted patch antenna results in the L–C circuit which is used to perform an impedance transformation for low noise amplifier. A 12 GHz low noise amplifier using L–C circuit can improve performance parameters as per designer’s requirement. A reconfigurable MOS loaded slotted patch antenna is verified using momentum microwave simulator and a wide bandwidth of 9 GHz in the frequency range of 10.3–19.3 GHz is achieved. The Low noise amplifier is simulated with TSMC 0.09 µm mixed signal/RF CMOS process technology. The post-layout circuit simulation results show that the proposed common source LNA with L–C network achieves a maximum power gain of 20 dB with the −3 dB bandwidth from the range of 10.3–13.6 GHz. A reflection coefficient of −14 dB and minimum noise figure of 1.6 dB is achieved. The power dissipation is 2.5 mW at 1.2 V supply voltage. Wireless Personal Communications Springer Journals

Design and Analysis of Low Noise Optimization Amplifier Using Reconfigurable Slotted Patch Antenna

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Springer US
Copyright © 2017 by Springer Science+Business Media, LLC
Engineering; Communications Engineering, Networks; Signal,Image and Speech Processing; Computer Communication Networks
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