Delta-sigma modulator with a 50-MHz sampling rate implemented in 0.18-μm CMOS technology

Delta-sigma modulator with a 50-MHz sampling rate implemented in 0.18-μm CMOS technology The results are presented of a design effort concerned with a delta-sigma modulator with a 50-MHz clock rate and a 128 oversampling ratio. Its prototype is fabricated in 0.18-μm CMOS technology and is powered by a 1.8-V unipolar supply. It provides a 9-bit resolution, while consuming 33 mW of power. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

Delta-sigma modulator with a 50-MHz sampling rate implemented in 0.18-μm CMOS technology

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Publisher
Springer Journals
Copyright
Copyright © 2010 by Pleiades Publishing, Ltd.
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1134/S106373971003008X
Publisher site
See Article on Publisher Site

Abstract

The results are presented of a design effort concerned with a delta-sigma modulator with a 50-MHz clock rate and a 128 oversampling ratio. Its prototype is fabricated in 0.18-μm CMOS technology and is powered by a 1.8-V unipolar supply. It provides a 9-bit resolution, while consuming 33 mW of power.

Journal

Russian MicroelectronicsSpringer Journals

Published: May 20, 2010

References

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