SOS structures with 0.1-and 0.3-μm-thick silicon layers were investigated with the method of thermally stimulated capacitor discharge. The effect of temperature, time, and several external factors on the parameters of deep traps in heteroepitaxial SOS layers was studied. The time-temperature exposures (conditions) were similar to those experienced by SOS structures used in CMOS/SOS LSI technology. It was shown that 0.1-and 0.3-μm-thick silicon layers grown on a sapphire substrate possess a high amount of recombination centers whose concentration does not change under various treatments (high-temperature annealing, laser annealing, and radiant treatment). This implies that traps due to process-related structure defects are of the same nature. The treatments used generate additional traps in the band gap. Low-temperature laser annealing and annealing at 950°C modify the trap spectrum to the greatest extent. It was also demonstrated that the concentration of deep traps in the 0.1-μm-thick silicon layers is more than one order of magnitude higher than in the 0.3-μm-thick layers and approaches the dopant concentration. The energy spectra of defects for as-grown and treated samples were derived
Russian Microelectronics – Springer Journals
Published: Dec 4, 2007
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