1063-7397/04/3305- © 2004 MAIK “Nauka /Interperiodica”
Russian Microelectronics, Vol. 33, No. 5, 2004, pp. 310–327. Translated from Mikroelektronika, Vol. 33, No. 5, 2004, pp. 379–398.
Original Russian Text Copyright © 2004 by Bibilo, Vasil’kova, Kardash, Kirienko, Loginova, Novikov, Romanov, Toropov, Cheremisinov, Cheremisinova.
With more than 10
logic gates per chip, the design
automation of custom very-large-scale-integration
(VLSI) circuits entails the application of scientiﬁc
knowledge. The design proceeds through a number of
speciﬁc phases that transform a behavioral speciﬁcation of
a circuit to a geometric-layout description for each of its
layers, the end result being pattern generation for actual
masks. In a logic-design phase, a behavioral description is
transformed into a network of combinational and sequen-
tial logic gates. This phase determines to a large extent the
ﬁgures of merit of the circuit such as overall layout area,
speed, testability, and complexity.
This paper describes the Custom Logic toolkit for
the complete computer-aided design (CAD) of VLSI
custom control logic, including the structure of the
toolkit and its interaction with other CAD systems. It
also discusses languages and procedures for different
THE PURPOSE AND FUNCTIONALITY
OF THE TOOLKIT
Custom Logic generates mask layouts for digital
the programmable logic array (PLA);
the Weinberger array;
the read-only memory (ROM);
the series metal–oxide–semiconductor (SMOS)
array, a form of programmable array logic.
To minimize layout area, a logic circuit can be
realized as a network of macros of different array
Custom Logic represents an improvement on the
SCAS silicon compiler, which can yield only single-
macro realizations . Furthermore, the synthesis and
veriﬁcation procedures employed in Custom Logic are
based on novel and efﬁcient optimization algorithms
and software for processing the behavioral and struc-
tural descriptions of project entities, the main optimiza-
tion criterion being layout area.
The user of Custom Logic can describe the behavior
and structure of project entities in a high-level lan-
guage, create hierarchical representations of projects,
and access design libraries.
Custom Logic deals with the following stages:
(i) algorithm design in a high-level language,
(ii) macro-type selection,
(iii) behavioral-description optimization for each
macro according to its type,
(iv) the logical veriﬁcation of a behavioral descrip-
tion for the whole circuit,
(v) structural-description synthesis and optimiza-
tion for each macro,
(vi) symbolic-layout generation and optimization
for each macro,
(vii) mask-layout generation for each macro.
Programmable Logic Array
The PLA consists of two arrays, known as the AND
plane and the OR plane, that implement a set of Boolean
functions speciﬁed in disjunctive normal form (DNF):
are the input variables (some of
them may be negated).
Below we consider an example of a PLA that serves
as a two-bit adder and consists of two half-adders, add1
Custom Logic: A Toolkit for the Design of VLSI Custom
Control MOS Logic
P. N. Bibilo, I. V. Vasil’kova, S. N. Kardash, N. A. Kirienko,
I. P. Loginova, Ya. A. Novikov,
V. I. Romanov, N. R. Toropov, D. I. Cheremisinov, and L. D. Cheremisinova
Joint Institute of Problems of Information Science, National Academy of Sciences of Belarus, Belarus
Received December 10, 2003
—The Custom Logic toolkit for the design of VLSI custom control MOS array logic is described. The
design phases supported range from the generation of behavioral and structural descriptions in high-level lan-
guages to mask-layout synthesis.
ELECTRONIC DESIGN AUTOMATION