Computer Evaluation of a Method for Combinational-Circuit Synthesis in FPGAs

Computer Evaluation of a Method for Combinational-Circuit Synthesis in FPGAs A method is proposed for the synthesis of combinational circuits in FPGAs subject to programmable-resource utilization. The method is evaluated by computer simulation. The circuit-optimization criterion is the degree of utilization of FPGA logic units and interconnects. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

Computer Evaluation of a Method for Combinational-Circuit Synthesis in FPGAs

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Publisher
Kluwer Academic Publishers-Plenum Publishers
Copyright
Copyright © 2004 by MAIK “Nauka/Interperiodica”
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1023/B:RUMI.0000011100.81232.da
Publisher site
See Article on Publisher Site

Abstract

A method is proposed for the synthesis of combinational circuits in FPGAs subject to programmable-resource utilization. The method is evaluated by computer simulation. The circuit-optimization criterion is the degree of utilization of FPGA logic units and interconnects.

Journal

Russian MicroelectronicsSpringer Journals

Published: Oct 18, 2004

References

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