1063-7397/04/3301- © 2004 MAIK “Nauka /Interperiodica”
Russian Microelectronics, Vol. 33, No. 1, 2004, pp. 46–54. Translated from Mikroelektronika, Vol. 33, No. 1, 2004, pp. 56–67.
Original Russian Text Copyright © 2004 by Shalagin.
Circuit design in programmable logic should draw
on structural and behavioral studies including the com-
plexity assessment in terms of both logic gates and
interconnects. Investigations have been reported into
the synthesis of combinational circuits in gate arrays
 and ﬁeld-programmable logic [2–4].
The present study is concerned with ﬁeld-program-
mable gate arrays (FPGAs) [5, 6]. In this context, an
actual combinational circuit is commonly evaluated in
terms of a given criterion, which must be below a given
level. Such a criterion may be the proportion of logic
units that are not fully utilized, including those serving as
interconnects . Also note that the choice of intercon-
nect conﬁguration affects the contribution of intercon-
nect delay to the total delay through the circuit [5, 6].
Below we argue for an approach to the evaluation of
combinational circuits implemented in FPGAs. The
evaluation is based on two criteria: (i) the proportion of
logic units that are not fully utilized, including those
serving as interconnects, and (ii) the interconnect delay
in relation to the total delay through the circuit.
In this study the method was applied to combina-
tional circuits implementing multiplication in a Galois
ﬁeld . An advantage of the model is that computation
can be realized as parallel processing, which suggests
using FPGAs. The evaluation was carried out with Xil-
inx Foundation Series 3.1i, a software system for the
computer-aided design of digital circuits .
THEORETICAL BASIS AND FORMULATION
OF THE PROBLEM
FPGAs are produced by the same technology as
static random-access memory based on complementary
metal–oxide–semiconductor ﬁeld-effect transistors.
The FPGA is a homogeneous system . It can be
reprogrammed many times, which enables the user to
make distinct circuits from the same FPGA [5, 6].
Being an array, the FPGA allows parallel processing. It
includes three groups of ﬁeld-programmable compo-
nents: input/output blocks (IOBs), conﬁgurable logic
blocks (CLBs), and interconnects [5, 6]. The CLB
implements a Boolean function of several variables .
of a CLB is deﬁned as the total num-
ber of its equivalent logic gates, each implementing a
Boolean function of two variables . Accordingly, a
CLB corresponding to a function of
variables has the
– 1. This study deals with FPGAs of the
XC4000E, Spartan, and XC5200 series, which typify
the technology .
With the XC4000E series, a CLB has two four-input
look-up tables (LUTs) and one three-input LUT; they
can implement any Boolean function of four or three
variables, respectively. Two inputs of the three-input
LUT are provided by the other LUTs of the CLB, while
one input comes from the outside. Alternatively, the
outputs of the four-input LUTs can be directed to other
CLBs. Thus, each CLB can implement a Boolean func-
tion of nine variables.
The Spartan series is more ﬂexible than XC4000E in
that the three-input LUT can receive all the three vari-
ables from the outside . With the XC5200 series, a
CLB has four four-input LUTs and so is roughly equiv-
alent to two CLBs of XC4000E .
The CLBs and interconnects of an FPGA might be
called the logical and wiring resources of the FPGA .
In this study, different FPGA realizations of a com-
binational circuit were evaluated in terms of logic
capacity and delay . A comparison was conducted
between realizations using the XC4000E, Spartan, and
XC5200 series, respectively. The theoretical basis of
this work is presented below.
Consider a homogeneous combina-
tional circuit that implements a set of Boolean func-
denoting the total number of
the circuit components utilized. The upper logic capac-
of the circuit is deﬁned as
Computer Evaluation of a Method for Combinational-Circuit
Synthesis in FPGAs
S. V. Shalagin
Kazan State Technical University, Kazan, Tatarstan, Russia
Received November 9, 2002
—A method is proposed for the synthesis of combinational circuits in FPGAs subject to programma-
ble-resource utilization. The method is evaluated by computer simulation. The circuit-optimization criterion is
the degree of utilization of FPGA logic units and interconnects.