CMOS logic elements with increased failure resistance to single-event upsets

CMOS logic elements with increased failure resistance to single-event upsets Two-phase submicron CMOS logic elements with a design standard of 0.18 μm are analyzed that are based on two symmetric signal transfer and conversion logical channels (phases). The basic elements of two-phase CMOS logic are 2- and 4-transistor CMOS converters that form two-phase inverters, NAND elements, and D and RS triggers. Two-phase CMOS inverters based on 2-transistor converters with transversely connected inputs and elements based on these inverters, NAND elements and D and RS triggers also with transversely connected constituent elements, are the best ones with respect to the set of parameters, including the failure resistance to single-event upsets (with respect to the value of the critical switching charge), size, and switching time. The values of the critical switching charges of the elements of two-phase CMOS logic under exposure to individual nuclear particles that induce ionization currents with fall-time constants (diffusion component) from 0.3 ns to 2.0 ns are determined. Russian Microelectronics Springer Journals

CMOS logic elements with increased failure resistance to single-event upsets

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SP MAIK Nauka/Interperiodica
Copyright © 2011 by Pleiades Publishing, Ltd.
Engineering; Electrical Engineering
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