CMOS logic elements with increased failure resistance to single-event upsets

CMOS logic elements with increased failure resistance to single-event upsets Two-phase submicron CMOS logic elements with a design standard of 0.18 μm are analyzed that are based on two symmetric signal transfer and conversion logical channels (phases). The basic elements of two-phase CMOS logic are 2- and 4-transistor CMOS converters that form two-phase inverters, NAND elements, and D and RS triggers. Two-phase CMOS inverters based on 2-transistor converters with transversely connected inputs and elements based on these inverters, NAND elements and D and RS triggers also with transversely connected constituent elements, are the best ones with respect to the set of parameters, including the failure resistance to single-event upsets (with respect to the value of the critical switching charge), size, and switching time. The values of the critical switching charges of the elements of two-phase CMOS logic under exposure to individual nuclear particles that induce ionization currents with fall-time constants (diffusion component) from 0.3 ns to 2.0 ns are determined. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

CMOS logic elements with increased failure resistance to single-event upsets

Loading next page...
 
/lp/springer_journal/cmos-logic-elements-with-increased-failure-resistance-to-single-event-D93HbtsWzh
Publisher
Springer Journals
Copyright
Copyright © 2011 by Pleiades Publishing, Ltd.
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1134/S106373971103005X
Publisher site
See Article on Publisher Site

Abstract

Two-phase submicron CMOS logic elements with a design standard of 0.18 μm are analyzed that are based on two symmetric signal transfer and conversion logical channels (phases). The basic elements of two-phase CMOS logic are 2- and 4-transistor CMOS converters that form two-phase inverters, NAND elements, and D and RS triggers. Two-phase CMOS inverters based on 2-transistor converters with transversely connected inputs and elements based on these inverters, NAND elements and D and RS triggers also with transversely connected constituent elements, are the best ones with respect to the set of parameters, including the failure resistance to single-event upsets (with respect to the value of the critical switching charge), size, and switching time. The values of the critical switching charges of the elements of two-phase CMOS logic under exposure to individual nuclear particles that induce ionization currents with fall-time constants (diffusion component) from 0.3 ns to 2.0 ns are determined.

Journal

Russian MicroelectronicsSpringer Journals

Published: May 22, 2011

References

You’re reading a free preview. Subscribe to read the entire article.


DeepDyve is your
personal research library

It’s your single place to instantly
discover and read the research
that matters to you.

Enjoy affordable access to
over 18 million articles from more than
15,000 peer-reviewed journals.

All for just $49/month

Explore the DeepDyve Library

Search

Query the DeepDyve database, plus search all of PubMed and Google Scholar seamlessly

Organize

Save any article or search result from DeepDyve, PubMed, and Google Scholar... all in one place.

Access

Get unlimited, online access to over 18 million full-text articles from more than 15,000 scientific journals.

Your journals are on DeepDyve

Read from thousands of the leading scholarly journals from SpringerNature, Elsevier, Wiley-Blackwell, Oxford University Press and more.

All the latest content is available, no embargo periods.

See the journals in your area

DeepDyve

Freelancer

DeepDyve

Pro

Price

FREE

$49/month
$360/year

Save searches from
Google Scholar,
PubMed

Create lists to
organize your research

Export lists, citations

Read DeepDyve articles

Abstract access only

Unlimited access to over
18 million full-text articles

Print

20 pages / month

PDF Discount

20% off