Characteristics of double-gate SOI CMOS nanotransistors for promising technologies with a low power consumption level

Characteristics of double-gate SOI CMOS nanotransistors for promising technologies with a low... A procedure, allowing one to optimize topological and electrophysical parameters of double gate SOI nanotransistors with a thin unalloyed working area, with underlap gate and drain/source regions with regard to the physical restrictions and process requirements, without recourse to the 2D-simulation, is considered. Based on the numerical simulation results, the selection criteria of the key topological parameters of transistors for implementing the requirements in accordance with the International Technology Roadmap for Semiconductor 2010 Edition program for promising applications with a low power consumption level are discussed. The complex analysis of the VACs of transistors and gate characteristics, such as a time switching delay, as well as active and static power, shows that prototypes of the considered units are applicable for implementing high-performance VLSI projects. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

Characteristics of double-gate SOI CMOS nanotransistors for promising technologies with a low power consumption level

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Publisher
SP MAIK Nauka/Interperiodica
Copyright
Copyright © 2013 by Pleiades Publishing, Ltd.
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1134/S1063739712060066
Publisher site
See Article on Publisher Site

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