Scalable high-efficiency video coding (SHVC) can provide variable video quality according to terminal devices. However, a computational complexity of SHVC is increased by introducing new techniques based on high-efficiency video coding (HEVC). In this paper, a hardware-oriented low complexity algorithm is proposed for the reference software of SHVC (SHM11.0). In our proposed algorithm, an optimal coding unit depth is determined by analyzing the boundary correlation in a coding tree unit before encoding starts. Simulation results show that the proposed algorithm can achieve over 62% computation complexity reduction comparing to the original SHM11.0. Compared with other related work, over 11% time saving has been achieved without PSNR loss. Moreover, to confirm the efficacy of the proposed algorithm, a hardware architecture is designed targeting on the CU depth decision algorithm. Synthesis results show that the hardware cost is about 1.8K gate and achieve a scalable working clock frequency in the case of FPGA (CycloneV) implementation.
Journal of Real-Time Image Processing – Springer Journals
Published: May 19, 2018
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