Aspect ratio of radiation-hardened MOS transistors

Aspect ratio of radiation-hardened MOS transistors The reliability of electronics in the proximity of the ionizing radiation is a key requirement in particular in high energy physics, nuclear power or space applications. One way to improve robustness of MOS transistors operating in such environments is to use enclosed layout techniques. This special layout approach helps to maintain leakage current of MOS transistors at low level even after irradiation, in contrast to a linear layout MOS transistor, where leakage current could increase by orders of magnitude. The issue, arising with enclosed layout transistors, is related to channel modelling, since the MOS transistor gate geometry is no more a simple rectangle. In this work, modelling of equivalent width and length dimensions of the MOS transistor channel under the gate is addressed. For this purpose transistors of four types and two layout versions, fabricated in a standard 180 nm CMOS process, are characterized. The accuracy of available models for equivalent channel dimensions is analysed, along with a new simplified geometrical model developed by the authors. They are further compared to the empirically extracted aspect ratio. The improvement possibilities for the considered models are then identified. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png e & i Elektrotechnik und Informationstechnik Springer Journals

Aspect ratio of radiation-hardened MOS transistors

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Publisher
Springer Journals
Copyright
Copyright © 2018 by The Author(s)
Subject
Engineering; Electrical Engineering; Computer Hardware; Software Engineering/Programming and Operating Systems
ISSN
0932-383X
eISSN
1613-7620
D.O.I.
10.1007/s00502-017-0575-2
Publisher site
See Article on Publisher Site

Abstract

The reliability of electronics in the proximity of the ionizing radiation is a key requirement in particular in high energy physics, nuclear power or space applications. One way to improve robustness of MOS transistors operating in such environments is to use enclosed layout techniques. This special layout approach helps to maintain leakage current of MOS transistors at low level even after irradiation, in contrast to a linear layout MOS transistor, where leakage current could increase by orders of magnitude. The issue, arising with enclosed layout transistors, is related to channel modelling, since the MOS transistor gate geometry is no more a simple rectangle. In this work, modelling of equivalent width and length dimensions of the MOS transistor channel under the gate is addressed. For this purpose transistors of four types and two layout versions, fabricated in a standard 180 nm CMOS process, are characterized. The accuracy of available models for equivalent channel dimensions is analysed, along with a new simplified geometrical model developed by the authors. They are further compared to the empirically extracted aspect ratio. The improvement possibilities for the considered models are then identified.

Journal

e & i Elektrotechnik und InformationstechnikSpringer Journals

Published: Jan 17, 2018

References

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