Application features of the error correction coding in sub-100-nm memory microcircuits for cosmic systems

Application features of the error correction coding in sub-100-nm memory microcircuits for cosmic... The studies performed in the process of designing error correction coding elements in sub-100-nm memory and microprocessor microcircuits confirm that the most efficiency of increasing upset tolerances of commercial RHBD memory microcircuits can be ensured by combining modern circuit solutions for memory elements and algorithmic data encoding and protection methods. Among the circuit methods, the following methods are urgent: the application of DICE memory cells for checking (reference) data files; the introduction of additional columns and multiplexers, intended to replace any column with an additional one, if a multiple incurable upset arises in this column; the implementation of data interleaving with a degree of no more than 8 s to minimize adjacent upsets in the code word. Algorithmic encoding approaches of (SEC-DED-DAEC) classes (single-error correction, double-error-detection, and double-adjacent-error-correction) are efficient for ensuring the upset tolerance of sub-100-nm very-largescale integration (VLSI) circuits under the external action of single nuclear particles. The encoding algorithm based on these recommendations demonstrated up to 27% better efficiency of correction of nonadjacent double errors at a slightly slower speed of operation and occupied on-chip area, as compared with Datta and Choi codes, thus allowing one to implement different implementation versions of upset tolerant VLSI circuits, depending on the solved problem. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

Application features of the error correction coding in sub-100-nm memory microcircuits for cosmic systems

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Publisher
SP MAIK Nauka/Interperiodica
Copyright
Copyright © 2013 by Pleiades Publishing, Ltd.
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1134/S1063739712040087
Publisher site
See Article on Publisher Site

Abstract

The studies performed in the process of designing error correction coding elements in sub-100-nm memory and microprocessor microcircuits confirm that the most efficiency of increasing upset tolerances of commercial RHBD memory microcircuits can be ensured by combining modern circuit solutions for memory elements and algorithmic data encoding and protection methods. Among the circuit methods, the following methods are urgent: the application of DICE memory cells for checking (reference) data files; the introduction of additional columns and multiplexers, intended to replace any column with an additional one, if a multiple incurable upset arises in this column; the implementation of data interleaving with a degree of no more than 8 s to minimize adjacent upsets in the code word. Algorithmic encoding approaches of (SEC-DED-DAEC) classes (single-error correction, double-error-detection, and double-adjacent-error-correction) are efficient for ensuring the upset tolerance of sub-100-nm very-largescale integration (VLSI) circuits under the external action of single nuclear particles. The encoding algorithm based on these recommendations demonstrated up to 27% better efficiency of correction of nonadjacent double errors at a slightly slower speed of operation and occupied on-chip area, as compared with Datta and Choi codes, thus allowing one to implement different implementation versions of upset tolerant VLSI circuits, depending on the solved problem.

Journal

Russian MicroelectronicsSpringer Journals

Published: Jan 4, 2013

References

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