The method of periodically doped channel was originally regarded as an application for transistor structures based on organic semiconductors. The possibility of channel conductivity modulation in CMOS transistors, however, is of high interest for high temperature electronics. To provide high conductivity of the nanoregions that reduce the overall effective length of the channel due to the geometric factor a the dope density in them must be high. However, the lateral drift of dope may result in closing of the doped nanoregions and in degradation of the subthreshold characteristics of the transistor. To handle this, as a dope additive (for the N channel of the MOS transistor), it is reasonable to use arsenic with its subsequent activation by rapid thermal annealing (RTA). Using programs for process simulation, we construct the device-technological model of a periodically doped channel field-effect transistor (PDCFET). This model allows one to solve the problem of technological implementation and characterization of the transitions manufactured in a 0.18–0.5 μm process with gate regions based on nanomasks which operate under extreme thermal conditions.
Russian Microelectronics – Springer Journals
Published: Jul 6, 2015
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