Int J Parallel Prog https://doi.org/10.1007/s10766-018-0578-6 An Area Efﬁcient and Low Power Consumption of Run Time Digital System Based on Dynamic Partial Reconﬁguration 1 2 R. Saravana Ram · A. Gopi Saminathan · S. Arun Prakash Received: 13 March 2018 / Accepted: 19 May 2018 © Springer Science+Business Media, LLC, part of Springer Nature 2018 Abstract Digital signal processing besides multimedia applications needs plenty of data, real-time processing capacity, and high computational power. Thus, adaptable architectures with run-time reconﬁguration abilities have gotten expanded considera- tion. Basically, Reconﬁguration computing is going towards advancing the application adaptability at runtime. A reconﬁgurable structure can be attained by working up the strategy aimed at conﬁguring an array of programmable logic reprogramming. Field Programmable Gate Arrays (FPGAs) is made with the intention of reconﬁguring the array system with interconnects as well as the conﬁguration of logic blocks. To imple- ment a high-performance FPGA device and also to enhance, the given paper proposes a proﬁcient design strategy. The proposed strategy count upon the employment of dynamic partial reconﬁguration (DPR) to drive from one mode then onto the next uti- lizing time-multiplexing on the same chip region. Furthermore, reconﬁgure modules to spare considerable area and enable the
International Journal of Parallel Programming – Springer Journals
Published: May 30, 2018
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