This paper proposes a new architecture of a time-to-digital converter (TDC) based on a self-timed ring (STR) oscillator with sub-gate delay resolution. The proposed TDC can virtually achieve as fine as desired time resolution by simply increasing its number of stages thanks to the STR unique features. Exploiting the phase difference between events propagating in the same STR without collision, this TDC benefit from a uniform phase distribution. Thus, under certain conditions, a regular time base can be generated and a compact readout algorithm can be applied. Moreover, the proposed technique allows on-the-fly time measurement on fast non-periodic signals. As a proof-of-concept, an STR-based TDC with only 9-stages has been simulated using 28 nm FDSOI technology. A time resolution of 8.9 ps has been achieved. Without using calibration, the measured DNL and INL are 0.44 and 0.40 LSB, respectively. Simulation results point out the advantage of this TDC in terms of measurement accuracy and state the limit of the on-the-fly measurement according to the dependency between the jitter and the time resolution.
Analog Integrated Circuits and Signal Processing – Springer Journals
Published: Jun 5, 2018
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