In this paper, amorphous silicon nanowires (α-SiNWs) were synthesized on (100) Si substrate with silicon oxide film by Cu catalyst-driven solid-liquid-solid mechanism (SLS) during annealing process (1080 °C for 30 min under Ar/H atmosphere). Micro size Cu pattern fabrication decided whether α-SiNWs can grow or not. Meanwhile, those micro size Cu patterns also controlled the position and density of wires. During the annealing process, Cu pattern reacted with SiO to form Cu silicide. More important, a diffusion channel was opened for Si atoms to synthesis α-SiNWs. What is more, the size of α-SiNWs was simply controlled by the annealing time. The length of wire was increased with annealing time. However, the diameter showed the opposite tendency. The room temperature resistivity of the nanowire was about 2.1 × 10 Ω·cm (84 nm diameter and 21 μm length). This simple fabrication method makes application of α-SiNWs become possible. Keywords: α-SiNWs, Cu patterns, Annealing time, Resistivity Background easily fabricate SiNW sensor devices. However, MEMS tech- Among the various classes of one-dimensional semicon- nique brings complex manufacture process with high cost. ductor nanostructure, silicon nanowire (SiNW) has been ex- In bottom-up approach, chemical vapor deposition hibited bright future in the fields of electronic, photovoltaic (CVD) is an important approach to synthesis SiNWs solar, photonic, battery, and sensor. [1–6] The SiNW with low-cost and simple fabrication process. And this manufacture method includes top-down and bottom-up ap- approach can readily produce extremely small diameter proaches. Table 1 is the summary of different SiNW manu- and super long SiNWs (as recorded, the smallest diam- facture method. Top-down approach is usually realized by eter was 1 nm, and the longest was millimeters) [14–16]. reactive ion etching (RIE) and metal-catalyzed electroless Good quality SiNWs are always synthesized through etching of silicon. In those methods, nanowire site is con- vapor-liquid-solid (VLS) mechanism with the help of Au trolled in top-down approach by nanofabrication tools such or other metals in this method . However, those novel as e-beam lithography,  nanoimprint lithography , or materials are prohibited in clean rooms for degrading nanosize template such as PS sphere,  AAO mask . the electrical and optical properties of semiconductors. Nanofabrication tools control the site, size, orientation, and Catalyst free method is put forward to solve pollution numbers of wire well with high-cost and complex fabrica- problem which brought by novel catalysts in bottom-up tion process. Nanosize template [9–11] is the low-cost approach. Oxide-assisted growth (OAG) method does not method, but the fabrication process is more complex than require any metal catalyst . Unfortunately, the compati- nanofabrication tool method for template should be built bility with Si-based integration technology is poor in this and removed during the whole process. Therefore, method. And products are always affected by other residual template-free method shows good potential in future . impurities easily . Room temperature continuous wave Another top-down approach uses MEMS technique to fab- laser ablation of Si is another way to synthesis SiNWs with- ricate site controllable SiNWs , this fabrication process out using metal catalyst . Nevertheless, high vacuum is needed. Even in the simple SiO evaporation technique, * Correspondence: email@example.com good size controllability is always hard to realize. Moreover, School of Electromechanical Engineering, Guangdong University of SiO powder is harmful to health . Technology, Guangzhou 510006, China Jiangsu Key Laboratory for Design and Manufacture of Micro-Nano Biomedical Instruments, Southeast University, Nanjing 211189, China © The Author(s). 2017 Open Access This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made. Yuan et al. Nanoscale Research Letters (2017) 12:487 Page 2 of 8 Table 1 Summary of different SiNW manufacture method Manufacture method Advantages Disadvantages References Top-down RIE The site and size of nanowires were Need nanofabrication tools. [7–10] well controlled. Metal-catalyzed electroless etching Template fabrication process was complex.  MEMS technique The site and size of nanowires were Complex fabrication process and  well controlled, without any time-consuming. nanofabrication tools. Bottom-up CVD Simple and low cost and the quality Novel metal materials were prohibited [14–16] of SiNW was good. in clean rooms. Controllability is poor. OAG Simple and low cost and no metal Controllability is poor. The compatibility [17, 18] catalyst is needed. with Si-based integration technology Laser ablation  was poor. SiO evaporation  New catalysts such as aluminum and copper are Methods researched to open the door of complementary metal Chip Fabrication oxide semiconductor (CMOS) technology to SiNWs First, 300 nm SiO film was grown on single side polished . Aluminum is used to reduce the deep level impur- n-type silicon (100) wafers by thermal oxidation (Fig. 1a). ities; it can also be a p-type dopant producing a shallow Then, 400 nm copper film was deposited on SiO by acceptor in Si. However, the high sensitivity to oxidation magnetron sputtering. After photolithographic process and makes using aluminum as catalyst method becoming un- ammonium persulfate solution (1:100 water) etching, Cu practical. Copper is a good conductor of heat and elec- micron-size pattern array were fabricated on SiO surface in tricity and has been widely used in integrated circuits target area (Fig. 1b). Subsequently, the wafer was diced into (ICs) and CMOS processing. So, copper is considered as chips. And those chips were ultrasonically cleaned by the suitable catalyst for SiNW growth. The size and site ethanol and acetone in turn for 10 min. Afterwards, DI of Si wires were well controlled by copper catalyst in water was used for last clean process before blow-dry by N . Kayes et al. work . In the works which copper was used as catalyst to synthesis SiNWs, SiH ,Si H , or SiCl α-SiNW Growth 4 2 6 4 gases were used as Si precursor [22–24]. One thousand standard cubic centimeters per minute of In this paper, we present a simple and effective method Ar was used to exclude air in the tube for 10 min after to synthesis SiNWs on SiO films by Cu catalyst-driven chips were put on quartz boat and transferred into the SLS mechanism during annealing process without using center of the horizontal furnace. any toxic precursor gases. This method has two advantages. Subsequently, five stages were used to synthesis SiNWs. Firstly, the metal contamination of the SiNWs was de- The detailed annealing processing conditions are given in creased. Secondly, no toxic precursor gases were used. Fig. 2. In stage I, the temperature was increased from Fig. 1 Schematic depiction of the fabrication process. a Thermal oxidation. b Cu micron-size pattern array fabrication. c Copper patterns changed into hemispheres. d Nanowire growth Yuan et al. Nanoscale Research Letters (2017) 12:487 Page 3 of 8 Fig. 2 Thermal processing conditions for SiNW synthesis using a horizontal furnace. In stage I, the temperature was increased from room temperature to 400 °C in 1 h with the same Ar flow which used to exclude air. In stage II, Ar flow was adjusted to 100 sccm, and 20 sccm H was added. It took 2 h to reach 1080 °C. In this stage, copper patterns changed into hemispheres. Then, temperature was held for 30 min with 1000 sccm Ar and 40 sccm H in stage III. After turning off the furnace, the fast cooling process only 10 min was taken as the IV stage and the flow was adjusted to 500 and 20 sccm respectively. In the last stage, slow cooling used to decrease the furnace temperature to room temperature with 100 sccm Ar and 20 sccm H room temperature to 400 °C in 1 h with the same Ar flow temperature to room temperature with 100 sccm Ar and which is used to exclude air. In stage II, Ar flow was 20 sccm H . After the five stages, α-SiNWs were grown adjusted to 100 sccm, and 20 sccm H was added. It took on the position of Cu patterns as shown in Fig. 1d. 2 h to reach 1080 °C. In this stage, copper patterns chan- ged into hemispheres (Fig. 1c). Then, temperature was held for 30 min with 1000 sccm Ar and 40 sccm H in Characterization stage III. After turning off the furnace, the fast cooling Scanning electron microscopy (SEM, Hitachi S-4800) process of only 10 min was taken as the IV stage and the and high-resolution transmission electron microscopy flow was adjusted to 500 and 20 sccm respectively. In the (TEM, JEM-2100F operating at 200 Kv) equipped with last stage, slow cooling used to decrease the furnace energy dispersive spectrometer (EDS) were employed for Fig. 3 SEM images for the two samples on 300 nm SiO surfacebeforeand after30 min annealed in Ar/H atmosphere at temperature 2 2 of 1080 °C. a Pre-annealed SEM image of sample I with Cu nanofilm (400 nm thick). b SEM images of sample I with Cu film after annealed. Inset photo was the diameter distribution of the Cu particles after SEM. c Pre-annealed SEM image of sample II with Cu patterns array (Cu pattern size, 400-nm thick and 1.9 μmdiameter). Inset photo was the magnified image of Cu patterns array. d SEM image of nanowire growth on sample II after annealed. Inset photo was the magnified image of nanowires. The scale bars in the insets are 10 μm Yuan et al. Nanoscale Research Letters (2017) 12:487 Page 4 of 8 Fig. 4 TEM images of nanowires. a TEM image of the tip part of nanowire. Inset photos were the selected area electron diffraction (SAED) of nanowire and the EDS spectrum respectively. The SAED pattern was obtained from the middle of the wire (white circle) in Fig. 4, and the aperture for SAED was 200 nm. b TEM image of nanowire. The inserted image was the detailed photo of nanowire in Fig. 4b analyzing the morphology and composition of the nano- 400 nm thick and 1.9 μm diameter, and center-to-center wires. For TEM measurements, Mo grid was used to pitch is 10 μm). It is obvious that the results of the two support nanowires. For FIB etching the root of the wire, samples were quite different after annealed at 1080 °C a thin layer of Au was evaporated on the surface to pro- for 30 min. For Cu film, shown in Fig. 3b, only Cu balls tect the wire by electron-beam-induced deposition were scattered randomly on the surface of SiO . The (EBID). Two-terminal device was used to measurement inserted figure in Fig. 3b was the diameter distributions the resistivity of nanowire . The wire was mechanic- of Cu balls, and the average diameter of the ball was ally removed from the substrate by nano-operator 4.4 μm. In-suit nanowire appeared in sample II after an- equipped on focused ion beam (FIB) (FEI, QUANTA3D nealing in Fig. 3d. The length of nanowire can be as long 600FIB System). Then, nanowire was weld on the two as 20 μm, and the diameter of nanowire is about 57 nm electrodes by Pt deposited with assisted electron beam. as shown in the inserted image of Fig. 3d. It is clear that Finally, the resistivity of the nanowire was measured by each pattern has grown one nanowire and the center-to- Cascade Semi-automatic probe station HP 4156. center distance equal to the value of Cu patterns. This means the density of nanowires can be controlled by Results and Discussion number of Cu patterns simply. The phenomenon in Figure 3 presents the SEM photos of two samples before Fig. 3 demonstrates that the micro size of Cu patterns and after annealing (sample I, the thick Cu film is are suitable for nanowire growth (in our case, the size of 400 nm, sample II is the Cu pattern arrays with size of Cu pattern was 400-nm thick and 1.9 μmdiameter). For Fig. 5 SEM images of α-SiNW root. a, b The SEM images of α-SiNW root part at tilt 45° after FIB etching. A long Si gap is found at the Si /SiO interface in (b) 2 Yuan et al. Nanoscale Research Letters (2017) 12:487 Page 5 of 8 Fig. 6 Schematic illustration of α-SiNW growth. During the annealing process, Cu patterns (a) dewet to the center of the pattern (b), and react with SiO to form Cu silicide (c). Then, Si atoms permeate into the Cu silicide. During this process, the different diffusion speed of Si atoms in the substrate which caused by the defect of substrate may induce the Si gap formation. When the dissolving Si atoms in silicide reached saturation, Si starts to precipitate to synthesis α-SiNWs (d) Cu film, dewetting effect happened at high temperature. reached saturation, Si starts to precipitate to synthesis α- In order to reduce the surface energy of Cu film, Cu balls SiNWs (Fig. 6d). were aggregated in random way (in Fig. 3b). It is clear that Cu has played a very important role in our The high-resolution transmission electron microscopy study. Something like black particle can be found at the tip (TEM) image in Fig. 4a reveals that the nanowire has a of the wire, although in most wires, this particle is not smooth morphology at diameter of 50 nm in sample II. existed. The mapping results (Fig. 7) show that no metal Thehighlydiffusive ring pattern(inset) of theselectedarea particle exists at the tip of the wire. The particle seems like electron diffraction (SAED) demonstrates that the nanowire themisunderstandingbythe angleof between thewireand was totally amorphous (in Fig. 4). Energy dispersive spec- holder, which was not suitable to observe. Unfortunately, trometer (EDS) results in Fig. 4 indicate that the wire con- no copper can be found at the root part of the wire (Fig. 5). sists of Si and O with atomic ratio of 4, which is far from the ratio of Si dioxide and suggests that a trace amount of oxygen exists in the SiNWs. For reduction atmosphere which was composed of Ar and H is maintained during nanowires growth process, so the light oxidiation only hap- pened during sample exposure to air after fabrication. After FIB etching the root part of thewireand substrate, cross section of the wire root was characterized by SEM with sample holder rotated 45°. It is interesting to find that the nanowire grown from the boundary between Si and SiO in Fig. 5. A long Si gap is also found at the Si /SiO 2 2 interface. Those observations demonstrate that the substrate was the only Si source for the wire. Meanwhile, no metal particle is found at the tip part of the wire. Ac- cording to those results, a possible schematic illustration of α-SiNW growth is presented in Fig. 6 based on solid-liquid- solid mechanism. During the annealing process, Cu pat- terns (Fig. 6a) dewet to the center of the pattern (Fig. 6b) and react with SiO to form Cu silicide (Fig. 6c). Then, Si 2 Fig. 7 TEM and EDS mapping images of the tip part of the atoms permeate into the Cu silicide. During this process, nanowire. a shows the TEM image of the tip part of the wire which seems like metal particle, b–d location of the different elements the different diffusion speed of Si atoms in the substrate illustrated by EDS mapping with bright contrast variation: copper which caused by the defect of substrate may induce the Si (b), silicon (c), and oxygen (d) gap formation. When the dissolving Si atoms in silicide Yuan et al. Nanoscale Research Letters (2017) 12:487 Page 6 of 8 Fig. 8 a–f The SEM images of α-SiNWs grown in different annealing time Cu diffusedintoSisubstratesisthe possible waythatmay seldom to see. Another interest finding is that the give rise to this surprising result. It is well known that fast diameter of root part was the bigger part in the whole diffusion of Cu atoms in Si was tested at high temperature wire, and the tip part was smaller (red arrows shown . So, Cu atoms could diffuse into Si substrate in a few in d–f). Comparing with the whole wire, the length of minutes after the window in SiO was opened at high nonuniform part is very short. This result presents temperature. that a-SiNW had nuniform diameter. To demonstrate the controllability of our method, dif- After SEM, the length and diameter of root part of α- ferent annealing time is carried out in our experiments. SiNWs are calculated. The results in Fig. 9 show that The SEM of nanowires synthesized in different annealing the length of α-SiNW was increased with annealing time with the same Cu pattern size (400-nm thick and time, as a function of the anneal time. The diffusion 1.9 um diameter) and same SiO thickness (300 nm) is time of Si atoms is increased offering more atoms to shown in Fig. 8. Most nanowires have uniform diameter. synthesis nanowire. The length of α-SiNW increases to It is interesting to find that the diameter decreased when 24 μm while the annealing time increased to 30 min. the direction of the wire changed. As red arrow shows in Fig. 8c, the tip part diameter is 76 nm, and the root part is only 49 nm. This huge difference in diameter in the same wire may be caused by the variation of the energy per unit area for the nucleus . And this phenomenon is Fig. 10 The electrical transport measurement of α-SiNW in Fig. 3. Two-terminal device was used to measure the resistivity of nanowire . The wire was mechanically removed from the substrate by nano-operator equipped on focused ion beam (FIB) (FEI, QUANTA3D 600FIB System). Then, nanowire was weld on the two electrodes by Fig. 9 The nanowire diameter and length as a function of the anneal Pt deposited with assisted electron beam. The resistivity of the time. Blue triangles and red circles in figure are the date for length and nanowire was measured by Cascade Semi-automatic probe station diameter of nanowire in experiment, and blue and red lines in figure HP 4156. Finally, the room temperature resistivity of the nanowire were the fitting line according to the experiment dates in Fig. 3 is 2.15 × 10 Ω·cm, measured by two-probe method Yuan et al. Nanoscale Research Letters (2017) 12:487 Page 7 of 8 The average growth rate of nanowire is approximately Publisher’sNote Springer Nature remains neutral with regard to jurisdictional claims in 1.1 μm/min, which was similar to the growth rate by published maps and institutional affiliations. annealing with block Si source . The rapid speed of growth is leaving no time for Si atoms to stack themselves Received: 5 April 2017 Accepted: 26 July 2017 into crystalline order. Finally, amorphous nanowires instead of crystalline are synthesized. The diameter of α-SiNW is decreased from 81 to References 1. Yu P, Wu J, Liu S, et al. (2016) Design and fabrication of silicon nanowires 57 nm in annealing time increasing process. Usually, the towards efficient solar cells. Nano Today length of SiNW depends on their diameter for Gibbs- 2. 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Published: Aug 10, 2017
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