Adaptive equalizer with a controller of a minimally admissible differential voltage of the output signal and pseudodifferential cascode output buffer for the 10-Gb/s transmitter according to the 65-nm CMOS technology

Adaptive equalizer with a controller of a minimally admissible differential voltage of the output... The adaptive equalizer presented in this article is developed as a component of a high-speed sequential transmitter used in a channel with a large signal damping coefficient. A controller integrated into this equalizer regulates the differential voltage of the output signal on the current correction depth of the intersymbol interference holding the specified minimally admissible differential voltage of the output signal invariable, which makes it possible to optimize the consumed power of the output buffer. A new in principle circuit of the pseudo-differential cascode output buffer with determinate jitter D J = 1.572 ps, peak output differential voltage V DIFFPPMAX = 1.9 V, and differential losses for reflection SDD22 =–8 dB at frequency F = 8.33 GHz is also developed for this equalizer. The equalizer is implemented according to the 65-nm CMOS technology providing data transfer at a rate of 10 Gb/s. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

Adaptive equalizer with a controller of a minimally admissible differential voltage of the output signal and pseudodifferential cascode output buffer for the 10-Gb/s transmitter according to the 65-nm CMOS technology

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Publisher
Pleiades Publishing
Copyright
Copyright © 2015 by Pleiades Publishing, Ltd.
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1134/S1063739715050066
Publisher site
See Article on Publisher Site

Abstract

The adaptive equalizer presented in this article is developed as a component of a high-speed sequential transmitter used in a channel with a large signal damping coefficient. A controller integrated into this equalizer regulates the differential voltage of the output signal on the current correction depth of the intersymbol interference holding the specified minimally admissible differential voltage of the output signal invariable, which makes it possible to optimize the consumed power of the output buffer. A new in principle circuit of the pseudo-differential cascode output buffer with determinate jitter D J = 1.572 ps, peak output differential voltage V DIFFPPMAX = 1.9 V, and differential losses for reflection SDD22 =–8 dB at frequency F = 8.33 GHz is also developed for this equalizer. The equalizer is implemented according to the 65-nm CMOS technology providing data transfer at a rate of 10 Gb/s.

Journal

Russian MicroelectronicsSpringer Journals

Published: Nov 4, 2015

References

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