ISSN 10637397, Russian Microelectronics, 2010, Vol. 39, No. 5, pp. 352–365. © Pleiades Publishing, Ltd., 2010.
Original Russian Text © V.V. Denisenko, 2010, published in Mikroelektronika, 2010, Vol. 39, No. 5, pp. 378–391.
Table models are a variety of compact models  and
represent a set of numerical data ordered in the form of
various array tables, as well as various methods of com
pression, decompression, and interpolation of these data.
Table models can reduce the simulation time by 20%
(www.cadence.com), there is no need to identify parame
ters for them, and they are very simple to develop. An
times was experimentally obtained,
when using a table model instead of an analytical model in
[2, 3]. The acceleration in comparison with the Level3
model of the Spice program is 16 times in , an acceler
ation of 6 times in comparison with the BSIM model 
is obtained in .
One of the most significant disadvantages of table
models is the complexity of the channel length and width
transformation, consideration of temperature influence,
and the inability of adjusting other parameters (for exam
ple threshold voltage and oxide thickness). A direct solu
tion of this problem is to construct a table with dimensions
equal to the number of controlled variables. However, this
alternative is now completely unacceptable in terms of
volume of stored data. Therefore, different ways of com
bining table modeling are used with analytic descriptions.
The adjustment of submicron transistors’ channel
length and width can be done with the help of several
tables for different values of
. To take into
account the geometry and temperature, 32 tables are used
in , 2 of which are used to store data for two values of the
channel width, and 4 tables are used to account for the
channel length. Accounting for variations in the techno
logical process is carried out by means of linear scaling
A similar problem related to the adjustment of param
eters exists when using a real transistor instead of its math
ematical model [8, 9].
The adjusting method of table and scaleddown model
parameters is suggested in this paper, which uses the
results of electrical tests (ET–tests) as initial data, which
can be performed in any silicon foundry during the mon
itoring of the technological process.
The adjustment of model parameters is necessary in
the following cases:
– to specify the sizes of a specific instance of a transis
tor within the VLSI;
– to transform the parameters of table models after
tuning the technological process;
– to solve multivariant problems (statistical calcula
tions, optimization, sensitivity analysis).
These tasks differ in the necessary range of the trans
formation of parameters. For example, an extremely wide
range of adjustment requires one to specify the sizes of a
specific transistor, but only two parameters, the channel
length and width, are controllable.
Parametric variation in a small range (up to
of the nominal value ) is enough for the adjust
ment of model parameters after tuning the technological
process, as well as for statistical analysis and sensitivity
analysis. For optimization problems, parameters need to
be changed over a wide range—but only two of them, the
, need to be changed.
Thus, to solve the most important problems of
VLSI schematic design, we need a wide range of trans
formation for parameters
and a small (up to
) tuning range for the transformation of param
eters (saturation current), (threshold voltage),
(coefficient of substrate influence),
(output resistance), which are used in technologi
cal process monitoring and adjustment.
THE CHANNEL LENGTH
AND WIDTH ADJUSTMENT
Table models set for transistors with various chan
nel lengths and widths (reference transistors) are con
structed for adjusting the channel length and width as
A Table MOS Transistor Model Parameter Control
V. V. Denisenko
Research Laboratory of Design Automation, Taganrog, Russia
email: victor@RLDA.ru, www.RealLab.ru
Received September 7, 2009
—The method for MOS transistor parameter control of submicron MOS transistors, which uses the
results of standard electronic testing carried out while monitoring the VLSI manufacturing process, is sug
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