A radiation-hard curvature compensated bandgap voltage reference

A radiation-hard curvature compensated bandgap voltage reference In this work a radiation-hardened bandgap voltage reference circuit is presented. The circuit is targeted at precision applications, where trimming can be used to achieve a temperature coefficient smaller than 5 ppm / K $5~\mbox{ppm}/\mbox{K}$ . Curvature compensation is employed and trimming of the temperature coefficient and the curvature is possible. In order to achieve good performance several techniques were combined. Radiation hardening techniques on layout level were used along with design techniques to improve the robustness against total ionizing dose (TID) and process variations. The radiation hardness requirements were set after preliminary irradiation tests. At the layout level optimized transistors were used while at the topology level, a radiation-hardened trimming scheme was employed to mitigate the impact of leakage currents. Chopping techniques were required to ensure good performance over the process and temperature variations. The bandgap was realized in a standard 180 nm CMOS process and circuit performance was verified using extensive simulations. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png e & i Elektrotechnik und Informationstechnik Springer Journals

A radiation-hard curvature compensated bandgap voltage reference

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Publisher
Springer Journals
Copyright
Copyright © 2018 by Springer-Verlag GmbH Austria, ein Teil von Springer Nature
Subject
Engineering; Electrical Engineering; Computer Hardware; Software Engineering/Programming and Operating Systems
ISSN
0932-383X
eISSN
1613-7620
D.O.I.
10.1007/s00502-018-0591-x
Publisher site
See Article on Publisher Site

Abstract

In this work a radiation-hardened bandgap voltage reference circuit is presented. The circuit is targeted at precision applications, where trimming can be used to achieve a temperature coefficient smaller than 5 ppm / K $5~\mbox{ppm}/\mbox{K}$ . Curvature compensation is employed and trimming of the temperature coefficient and the curvature is possible. In order to achieve good performance several techniques were combined. Radiation hardening techniques on layout level were used along with design techniques to improve the robustness against total ionizing dose (TID) and process variations. The radiation hardness requirements were set after preliminary irradiation tests. At the layout level optimized transistors were used while at the topology level, a radiation-hardened trimming scheme was employed to mitigate the impact of leakage currents. Chopping techniques were required to ensure good performance over the process and temperature variations. The bandgap was realized in a standard 180 nm CMOS process and circuit performance was verified using extensive simulations.

Journal

e & i Elektrotechnik und InformationstechnikSpringer Journals

Published: Feb 9, 2018

References

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