A new technology for manufacturing the dielectric isolation of elements of microelectronic devices by oxidizing grooves in single-crystal silicon

A new technology for manufacturing the dielectric isolation of elements of microelectronic... The formation of the dielectric isolation of elements of microelectronic devices by oxidizing grooves in single-crystal silicon is considered. The new technological process makes it possible to shorten the manufacturing cycle and to improve the reliability and parameters of devices. It is shown that this result is attained by substantially shortening the time of oxidation of silicon, suppressing the “bird’s beak” irregularity, and reducing the capacitance of the metal-insulator-semiconductor structure through the etching of grooves with certain geometric parameters in silicon nitride. These parameters are the groove width 0.5–1.5 μm, the ratio of the width to the spacing between the grooves 0.56: 0.44, and the groove depth, which is larger than the width. The results of two-dimensional physical simulation support the advantages of the new technology over the standard process. The simulation was accomplished with the use of the SSUPREM4 program of the Silvaco bundled software. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

A new technology for manufacturing the dielectric isolation of elements of microelectronic devices by oxidizing grooves in single-crystal silicon

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Publisher
SP MAIK Nauka/Interperiodica
Copyright
Copyright © 2010 by Pleiades Publishing, Ltd.
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1134/S1063739710010026
Publisher site
See Article on Publisher Site

Abstract

The formation of the dielectric isolation of elements of microelectronic devices by oxidizing grooves in single-crystal silicon is considered. The new technological process makes it possible to shorten the manufacturing cycle and to improve the reliability and parameters of devices. It is shown that this result is attained by substantially shortening the time of oxidation of silicon, suppressing the “bird’s beak” irregularity, and reducing the capacitance of the metal-insulator-semiconductor structure through the etching of grooves with certain geometric parameters in silicon nitride. These parameters are the groove width 0.5–1.5 μm, the ratio of the width to the spacing between the grooves 0.56: 0.44, and the groove depth, which is larger than the width. The results of two-dimensional physical simulation support the advantages of the new technology over the standard process. The simulation was accomplished with the use of the SSUPREM4 program of the Silvaco bundled software.

Journal

Russian MicroelectronicsSpringer Journals

Published: Jan 21, 2010

References

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