A continuous-time delta-sigma ADC for portable ultrasound scanners

A continuous-time delta-sigma ADC for portable ultrasound scanners A fully differential fourth-order 1-bit continuous-time delta-sigma ADC designed in a 65 nm process for portable ultrasound scanners is presented in this paper. The circuit design, implementation and measurements on the fabricated die are shown. The loop filter consists of RC-integrators, programmable capacitor arrays, resistors and voltage feedback DACs. The quantizer contains a pulse generator, a high-speed clocked comparator and a pull-down clocked latch to ensure constant delay in the feedback loop. Using this implementation, a small and low-power solution required for portable ultrasound scanner applications is achieved. The converter has a supply voltage of 1.2 V, a bandwidth of 10 MHz and an oversampling ratio of 16 leading to an operating frequency of 320 MHz. The design occupies a die area of $$0.0175\hbox { mm}^2$$ 0.0175 mm 2 . Simulations with extracted parasitics show a SNR of 45.2 dB and a current consumption of $$489 \,\upmu \hbox {A}$$ 489 μ A . However, by adding a model of the measurement setup used, the performance degrades to 42.1 dB. The measured SNR and current consumption are 41.6 dB and $$495\,\upmu \hbox {A}$$ 495 μ A , which closely fit with the expected simulations. Several dies have been measured, and an estimation of the die spread distribution is given. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Analog Integrated Circuits and Signal Processing Springer Journals

A continuous-time delta-sigma ADC for portable ultrasound scanners

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Publisher
Springer US
Copyright
Copyright © 2017 by Springer Science+Business Media, LLC
Subject
Engineering; Circuits and Systems; Electrical Engineering; Signal,Image and Speech Processing
ISSN
0925-1030
eISSN
1573-1979
D.O.I.
10.1007/s10470-017-1004-5
Publisher site
See Article on Publisher Site

Abstract

A fully differential fourth-order 1-bit continuous-time delta-sigma ADC designed in a 65 nm process for portable ultrasound scanners is presented in this paper. The circuit design, implementation and measurements on the fabricated die are shown. The loop filter consists of RC-integrators, programmable capacitor arrays, resistors and voltage feedback DACs. The quantizer contains a pulse generator, a high-speed clocked comparator and a pull-down clocked latch to ensure constant delay in the feedback loop. Using this implementation, a small and low-power solution required for portable ultrasound scanner applications is achieved. The converter has a supply voltage of 1.2 V, a bandwidth of 10 MHz and an oversampling ratio of 16 leading to an operating frequency of 320 MHz. The design occupies a die area of $$0.0175\hbox { mm}^2$$ 0.0175 mm 2 . Simulations with extracted parasitics show a SNR of 45.2 dB and a current consumption of $$489 \,\upmu \hbox {A}$$ 489 μ A . However, by adding a model of the measurement setup used, the performance degrades to 42.1 dB. The measured SNR and current consumption are 41.6 dB and $$495\,\upmu \hbox {A}$$ 495 μ A , which closely fit with the expected simulations. Several dies have been measured, and an estimation of the die spread distribution is given.

Journal

Analog Integrated Circuits and Signal ProcessingSpringer Journals

Published: Jun 29, 2017

References

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