A CMOS MF energy harvesting and data demodulator receiver for wide area low duty cycle applications with 250mV start-up voltage

A CMOS MF energy harvesting and data demodulator receiver for wide area low duty cycle... A low voltage start-up energy harvesting medium frequency receiver is presented, for use as the power and synchronisation part of a remote sensor node in a wide area industrial or agricultural application. The use of embedded low bandwidth network synchronisation data permits very low operational duty cycle without the need for real time clocks or wake up receivers at each node with their associated continuous power drain. The receiver consists of a rectifier, a power management unit and a phase-shift keying demodulator. The rectifier is optimised for low start-up and operating voltage rather than power efficiency. With standard MOS thresholds the rectifier can cold start with only 250 mV peak antenna input, and useful battery charging is delivered with 330 mV peak input. The QPSK demodulator consumes 1.27 μW with a supply voltage of 630 mV at a data rate of 1.6 kbps with 1 MHz carrier frequency. The IC is implemented in a standard threshold 0.18 μm CMOS technology, occupies 0.54 mm2 and can deliver 10.3 μW at 3 V to an external battery or capacitor. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Analog Integrated Circuits and Signal Processing Springer Journals

A CMOS MF energy harvesting and data demodulator receiver for wide area low duty cycle applications with 250mV start-up voltage

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Publisher
Springer US
Copyright
Copyright © 2017 by The Author(s)
Subject
Engineering; Circuits and Systems; Electrical Engineering; Signal,Image and Speech Processing
ISSN
0925-1030
eISSN
1573-1979
D.O.I.
10.1007/s10470-017-1000-9
Publisher site
See Article on Publisher Site

Abstract

A low voltage start-up energy harvesting medium frequency receiver is presented, for use as the power and synchronisation part of a remote sensor node in a wide area industrial or agricultural application. The use of embedded low bandwidth network synchronisation data permits very low operational duty cycle without the need for real time clocks or wake up receivers at each node with their associated continuous power drain. The receiver consists of a rectifier, a power management unit and a phase-shift keying demodulator. The rectifier is optimised for low start-up and operating voltage rather than power efficiency. With standard MOS thresholds the rectifier can cold start with only 250 mV peak antenna input, and useful battery charging is delivered with 330 mV peak input. The QPSK demodulator consumes 1.27 μW with a supply voltage of 630 mV at a data rate of 1.6 kbps with 1 MHz carrier frequency. The IC is implemented in a standard threshold 0.18 μm CMOS technology, occupies 0.54 mm2 and can deliver 10.3 μW at 3 V to an external battery or capacitor.

Journal

Analog Integrated Circuits and Signal ProcessingSpringer Journals

Published: Jul 5, 2017

References

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