A circuit implementation of a single-bit CMOS adder

A circuit implementation of a single-bit CMOS adder In this article, a circuit implementation of a single-bit CMOS adder with enhanced performance is presented. The adder circuit consists of separate circuits operating in-parallel for obtaining the output sum and carry signals. The carry circuit signal is not used to form the sum signal. The sum signal circuit is a sequential connection of two XOR cells. The circuit operability is confirmed by the results of circuit simulation using Cadence Design Systems’ software. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

A circuit implementation of a single-bit CMOS adder

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Publisher
SP MAIK Nauka/Interperiodica
Copyright
Copyright © 2013 by Pleiades Publishing, Ltd.
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1134/S106373971302008X
Publisher site
See Article on Publisher Site

Abstract

In this article, a circuit implementation of a single-bit CMOS adder with enhanced performance is presented. The adder circuit consists of separate circuits operating in-parallel for obtaining the output sum and carry signals. The carry circuit signal is not used to form the sum signal. The sum signal circuit is a sequential connection of two XOR cells. The circuit operability is confirmed by the results of circuit simulation using Cadence Design Systems’ software.

Journal

Russian MicroelectronicsSpringer Journals

Published: Mar 13, 2013

References

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