A highly energy-efficient, highly area-efficient asymmetric capacitance switching scheme for successive approximation register (SAR) analog-to-digital converters (ADC) is presented. Based on the monotonic switching procedure and asymmetric capacitance array, the novel architecture achieves 97.65% reduction in capacitor area over the conventional SAR ADC. Besides, with the split-capacitor method and most significant bit split switching procedure, the proposed switching scheme achieves 99.77% less switching energy compared with the conventional switching method.
Analog Integrated Circuits and Signal Processing – Springer Journals
Published: May 28, 2018
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