A 0.18 $$\upmu$$ μ m CMOS voltage multiplier arrangement for RF energy harvesting

A 0.18 $$\upmu$$ μ m CMOS voltage multiplier arrangement for RF energy harvesting This work presents a two-stage voltage multiplier (VM) useful in RF energy harvesting based applications. The proposed circuit is based on the conventional differential drive rectifier, in which the input RF signal has been level shifted using a simple arrangement. This signal is then used to drive the next stage, which has been formed by using gate cross-coupled transistors. As a result, the load driving capability of the proposed architecture increases. The load in this work has been emulated in terms of a parallel RC circuit. The architecture has been implemented using standard 0.18  $$\mu$$ μ m CMOS technology. The measurements of the two-stage conventional VM (CVM) and proposed VM circuits were performed at ISM frequencies 13.56, 433, 915 MHz and 2.4 GHz for R $$_L$$ L of values 1, 5, 10, 3 and 100 K $$\Omega$$ Ω with a fixed value of C $$_L$$ L equal to 20 pF. The performance evaluation has been done in terms of the power conversion efficiency (PCE) and average output DC voltage. The measured results show an improvement in PCE of 5% (minimum) for 13.56, 433 and 915 MHz frequencies, and up to 2% improvement for a frequency value of 2.4 GHz at the targeted load condition of 5 K $$\Omega ||$$ Ω | | 20 pF, when compared with the measured results of the CVM circuit. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Analog Integrated Circuits and Signal Processing Springer Journals

A 0.18 $$\upmu$$ μ m CMOS voltage multiplier arrangement for RF energy harvesting

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Publisher
Springer US
Copyright
Copyright © 2017 by Springer Science+Business Media, LLC
Subject
Engineering; Circuits and Systems; Electrical Engineering; Signal,Image and Speech Processing
ISSN
0925-1030
eISSN
1573-1979
D.O.I.
10.1007/s10470-017-1001-8
Publisher site
See Article on Publisher Site

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