Sensitivity characteristics of the DICE CMOS memory cells as two-phase D triggers with the 65-nm design rule. The dependences of critical values of the amplitudes of current pulses causing the failures during recording and storing the data are determined for various coupling capacitances of differential inputs of two-phase inverters in the composition of the memory cell. The following limitations for the values of these capacitances are established: 0.4–0.5 fF for memory cells based on NMOS transistors with a channel width of 400 nm and 0.2–0.3 fF for NMOS transistors with a channel width of 120 nm. Evaluations of critical integral charges that characterize the failure tolerance under the effect of separate nuclear particles give correspondingly values of 25–20 fC, which is larger by a factor of 8 compared with the 6-transistor CMOS memory cells.
Russian Microelectronics – Springer Journals
Published: Jul 12, 2012
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