A new manufacturing process is proposed and evaluated for CMOS memory circuits that is designed to decrease labor input and to increase yield. It essentially uses thermal silicon dioxide instead of silicon nitride as the material of the mask for n −- and p −-wells, and employs an improved doping procedure for the wells. The new process is shown to decrease considerably the residual stress and defect density in the wafer. Its advantages over the standard process are supported by a two-dimensional computer simulation with Silvaco’s SSUPREM4.
Russian Microelectronics – Springer Journals
Published: May 27, 2008
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