Limitations and prospects of using the two-phase CMOS logics in upset-immune sub-100-nm VLSIs

Limitations and prospects of using the two-phase CMOS logics in upset-immune sub-100-nm VLSIs The upset immunity of CMOS inverters with a two-phase structure to the effect of single nuclear particles for inverters with 65-nm and 45-nm design rules substantially depends on the capacitive coupling of their differential inputs (outputs). To evaluate the upset immunity, threshold characteristics are suggested, which associate the threshold values of critical charges with the corresponding threshold values of the capacity of the differential coupling. With the capacities of the differential coupling lower than the threshold values, the critical charges of two-phase CMOS inverters exceed the critical charges of the conventional CMOS logics by a factor of more than 10. Critical charges have lower values under the effect of current pulses with small constant rise and fall times. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

Limitations and prospects of using the two-phase CMOS logics in upset-immune sub-100-nm VLSIs

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Publisher
Springer Journals
Copyright
Copyright © 2014 by Pleiades Publishing, Ltd.
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1134/S1063739714020115
Publisher site
See Article on Publisher Site

Abstract

The upset immunity of CMOS inverters with a two-phase structure to the effect of single nuclear particles for inverters with 65-nm and 45-nm design rules substantially depends on the capacitive coupling of their differential inputs (outputs). To evaluate the upset immunity, threshold characteristics are suggested, which associate the threshold values of critical charges with the corresponding threshold values of the capacity of the differential coupling. With the capacities of the differential coupling lower than the threshold values, the critical charges of two-phase CMOS inverters exceed the critical charges of the conventional CMOS logics by a factor of more than 10. Critical charges have lower values under the effect of current pulses with small constant rise and fall times.

Journal

Russian MicroelectronicsSpringer Journals

Published: Mar 26, 2014

References

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