Access the full text.
Sign up today, get DeepDyve free for 14 days.
Loading next page...
/lp/springer-journals/designing-tsvs-for-3d-integrated-circuits-tsvs-for-power-delivery-CFRa284flq
References (113)
-
E. Wong, S. Lim (2006)
3D Floorplanning with Thermal ViasProceedings of the Design Automation & Test in Europe Conference, 1
-
N. Srivastava, R. Joshi, K. Banerjee (2005)
Carbon nanotube interconnects: implications for performance, power dissipation and thermal managementIEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.
-
M. Miao, Yufeng Jin, Hongguang Liao, Liwei Zhao, Yunhui Zhu, Xin Sun, Y. Guo (2009)
Research on deep RIE-based through-Si-via micromachining for 3-D system-in-package integration2009 4th IEEE International Conference on Nano/Micro Engineered and Molecular Systems
-
R. Montoye (2004)
The four degrees of 3D -
Y. Kurita, K. Soejima, K. Kikuchi, M. Takahashi, M. Tago, M. Koike, L. Shibuya, S. Yamamichi, M. Kawano (2006)
A novel "SMAFTI" package for inter-chip wide-band data transfer56th Electronic Components and Technology Conference 2006
-
Joyce Wu (2006)
Through-substrate interconnects for 3-D integration and RF systems -
R. Patti (2006)
Three-Dimensional Integrated Circuits and the Future of System-on-Chip DesignsProceedings of the IEEE, 94
-
M. Schulz (1999)
The end of the road for silicon?Nature, 399
-
M. Beattie, L. Pileggi (2001)
Inductance 101: modeling and extractionProceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)
-
Y. Massoud, A. Nieuwoudt (2006)
Modeling and design challenges and solutions for carbon nanotube-based interconnect in future high performance integrated circuitsACM J. Emerg. Technol. Comput. Syst., 2
-
A. Naeemi, J. Meindl (2007)
Carbon nanotube interconnects -
Lingbo Zhu, Jianwen Xu, Y. Xiu, Yangyang Sun, D. Hess, C. Wong (2006)
Growth and electrical characterization of high-aspect-ratio carbon nanotube arraysCarbon, 44
-
Yong Zhan, Tianpei Zhang, S. Sapatnekar (2007)
Module assignment for pin-limited designs under the stacked-Vdd paradigm2007 IEEE/ACM International Conference on Computer-Aided Design
-
Hao Yu, J. Ho, Lei He (2009)
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrityACM Trans. Design Autom. Electr. Syst., 14
-
K. Banerjee, N. Srivastava (2006)
Are carbon nanotubes the future of VLSI interconnections?2006 43rd ACM/IEEE Design Automation Conference
-
D.Y. Chen, W. Chiou, M.F. Chen, T. Wang, K. Ching, H. Tu, W.J. Wu, C. Yu, K. Yang, H.B. Chang, M. Tseng, C.W. Hsiao, Y.J. Lu, H. Hu, Y.C. Lin, C. Hsu, W. Shue, C. Yu (2009)
Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking2009 IEEE International Electron Devices Meeting (IEDM)
-
Young-Joon Lee, Y. Kim, Gang Huang, M. Bakir, Y. Joshi, A. Fedorov, S. Lim (2009)
Co-design of signal, power, and thermal distribution networks for 3D ICs2009 Design, Automation & Test in Europe Conference & Exhibition
-
J. Cong, Yan Zhang (2005)
Thermal-driven multilevel routing for 3D ICsProceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005., 1
-
G. Duesberg, A. Graham, F. Kreupl, M. Liebau, R. Seidel, E. Unger, W. Hoenlein (2003)
Ways towards the scaleable integration of carbon nanotubes into silicon based technologyDiamond and Related Materials, 13
-
D. Jang, Chunghyun Ryu, Kwangyong Lee, B. Cho, Joungho Kim, Taesung Oh, W. Lee, Jin Yu (2007)
Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV)2007 Proceedings 57th Electronic Components and Technology Conference
-
R. Nagarajan, L. Ebin, Lee Dayong, Soh Seng, K. Prasad, N. Balasubramanian (2006)
Development of a novel deep silicon tapered via etch process for through-silicon interconnection in 3-D integrated systems56th Electronic Components and Technology Conference 2006
-
C. Patel (2006)
Silicon carrier for computer systems2006 43rd ACM/IEEE Design Automation Conference
-
M. Cantoro, S. Hofmann, S. Pisana, V. Scardaci, A. Parvez, C. Ducati, A. Ferrari, A. Blackburn, Kaiyuan Wang, J. Robertson (2006)
Catalytic chemical vapor deposition of single-wall carbon nanotubes at low temperatures.Nano letters, 6 6
-
B. Wei, R. Vajtai, P. Ajayan (2001)
Reliability and current carrying capacity of carbon nanotubesApplied Physics Letters, 79
-
J. Early (1960)
Speed, power and component density in multielement high-speed logic systems -
S. Pozder, J. Lu, Y. Kwon, S. Zollner, J. Yu, J. McMahon, T. Cale, K. Yu, R. Gutmann (2004)
Back-end compatibility of bonding and thinning processes for a wafer-level 3D interconnect technology platformProceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)
-
Jonghyun Cho, J. Shim, Eakhwan Song, J. Pak, Junho Lee, Hyungdong Lee, Kunwoo Park, Joungho Kim (2009)
Active circuit to through silicon via (TSV) noise coupling2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems
-
R. Baughman, A. Zakhidov, W. Heer (2002)
Carbon Nanotubes--the Route Toward ApplicationsScience, 297
-
P. McEuen, Ji-Yong Park (2004)
Electron Transport in Single-Walled Carbon NanotubesMRS Bulletin, 29
-
L. Zheng, Michael O'Connell, S. Doorn, X. Liao, Yonghao Zhao, Elshan Akhadov, M. Hoffbauer, B. Roop, Q. Jia, R. Dye, Dean Peterson, Shaoming Huang, Jie Liu, Yun-tian Zhu (2004)
Ultralong single-wall carbon nanotubesNature Materials, 3
-
J. Minz, S. Lim, Cheng-Kok Koh (2005)
3D module placement for congestion and power noise reductionProceedings of the 15th ACM Great Lakes symposium on VLSI
-
Yuan Xie, J. Cong, S. Sapatnekar (2010)
Three Dimensional Integrated Circuit Design -
J. Knickerbocker, C. Patel, P. Andry, C. Tsang, L. Buchwalter, E. Sprogis, H. Gan, R. Horton, R. Polastre, S. Wright, J. Cotte (2006)
3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-ViasIEEE Journal of Solid-State Circuits, 41
-
P. Andry, C. Tsang, B. Webb, E. Sprogis, S. Wright, B. Dang, D. Manzer (2008)
Fabrication and characterization of robust through-silicon vias for silicon-carrier applicationsIBM J. Res. Dev., 52
-
G. Moore (2003)
No exponential is forever: but "Forever" can be delayed! [semiconductor industry]2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.
-
Ji-Yong Park, S. Rosenblatt, Y. Yaish, V. Sazonova, Hande Ustunel, S. Braig, T. Arias, P. Brouwer, P. McEuen (2003)
Electron-Phonon Scattering in Metallic Single-Walled Carbon NanotubesNano Letters, 4
-
W. Wang, S. Haruehanroengra, Liwei Shang, Mei Liu (2007)
Inductance of mixed carbon nanotube bundlesMicro & Nano Letters, 2
-
C. Selvanayagam, Xiaowu Zhang, R. Rajoo, D. Pinjala (2009)
Modelling stress in silicon with TSVs and its effect on mobility2009 11th Electronics Packaging Technology Conference
-
J. Keinert, M. Streubühr, T. Schlichter, J. Falk, J. Gladigau, C. Haubelt, J. Teich, M. Meredith (2009)
SystemCoDesigner—an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applicationsACM Trans. Design Autom. Electr. Syst., 14
-
M. Rousseau, M. Jaud, Patrick Leduc, Alexis Farcy, Antoine Marty (2009)
Impact of substrate coupling induced by 3D-IC architecture on advanced CMOS technology2009 European Microelectronics and Packaging Conference
-
J. Joyner, R. Venkatesan, P. Zarkesh-Ha, Jeffrey Davis, J. Meindl (2001)
Impact of three-dimensional architectures on interconnects in gigascale integrationIEEE Trans. Very Large Scale Integr. Syst., 9
-
J. Knickerbocker, P. Andry, B. Dang, R. Horton, M. Interrante, C. Patel, R. Polastre, K. Sakuma, R. Sirdeshmukh, E. Sprogis, S. Sri-Jayantha, Antonio Stephens, Anna Topol, C. Tsang, B. Webb, S. Wright (2008)
Three-dimensional silicon integrationIBM J. Res. Dev., 52
-
Gang Huang, M. Bakir, A. Naeemi, H. Chen, J. Meindl (2007)
Power Delivery for 3D Chip Stacks: Physical Modeling and Design Implication2007 IEEE Electrical Performance of Electronic Packaging
-
C. Laviron, B. Dunne, V. Lapras, P. Galbiati, D. Henry, F. Toia, S. Moreau, R. Anciant, C. Brunet-Manquat, N. Sillon (2009)
Via first approach optimisation for Through Silicon Via applications2009 59th Electronic Components and Technology Conference
-
N. Golshani, J. Derakhshandeh, R. Ishihara, K. Beenakker, M. Robertson, T. Morrison (2010)
Monolithic 3D integration of SRAM and image sensor using two layers of single grain silicon2010 IEEE International 3D Systems Integration Conference (3DIC)
-
H. Stahl, J. Appenzeller, R. Martel, Ph. Avouris, B. Aachen, Germany, Ibm Center, Ny, Usa (2000)
Intertube coupling in ropes of single-wall carbon nanotubesPhysical review letters, 85 24
-
P. Burke (2002)
Luttinger liquid theory as a model of the gigahertz electrical properties of carbon nanotubesIEEE Transactions on Nanotechnology, 1
-
K. Banerjee, Sungjun Im, N. Srivastava (2005)
Interconnect Modeling and Analysis in the Nanometer Era: Cu and Beyond -
B. Vandevelde, C. Okoro, M. Gonzalez, B. Swinnen, E. Beyne (2008)
Thermo-mechanics of 3D-wafer level and 3D stacked IC packaging technologiesEuroSimE 2008 - International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Micro-Systems
-
K. Banerjee, Hong Li, N. Srivastava (2008)
Current Status and Future Perspectives of Carbon Nanotube Interconnects2008 8th IEEE Conference on Nanotechnology
-
S. Denda (2007)
Process Examination of Through Silicon Via TechnologiesPolytronic 2007 - 6th International Conference on Polymers and Adhesives in Microelectronics and Photonics
-
Huaixing Li, Wengang Lu, J. Li, X. Bai, C. Gu (2005)
Multichannel ballistic transport in multiwall carbon nanotubes.Physical review letters, 95 8
-
H. Ishikuro, N. Miura, T. Kuroda (2007)
Wideband Inductive-coupling Interface for High-performance Portable System2007 IEEE Custom Integrated Circuits Conference
-
G. Moore (1998)
Cramming More Components Onto Integrated CircuitsProceedings of the IEEE, 86
-
E. Beyne (2008)
Solving Technical and Economical Barriers to the Adoption of Through-Si-Via 3D Integration Technologies2008 10th Electronics Packaging Technology Conference
-
Annick Loiseau, P. Launois, P. Petit, S. Roche, J. Salvetat (2006)
Understanding carbon nanotubes : from basics to applications -
M. Motoyoshi (2009)
Through-Silicon Via (TSV)Proceedings of the IEEE, 97
-
M. Bakir, C. King, D. Sekar, H. Thacker, B. Dang, Gang Huang, A. Naeemi, J. Meindl (2008)
3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation2008 IEEE Custom Integrated Circuits Conference
-
G. Loh, Yuan Xie, B. Black (2007)
Processor Design in 3D Die-Stacking TechnologiesIEEE Micro, 27
-
Hao Yu, J. Ho, Lei He (2006)
Simultaneous Power and Thermal Integrity Driven Via Stapling in 3D ICs2006 IEEE/ACM International Conference on Computer Aided Design
-
M. Nihei, D. Kondo, A. Kawabata, S. Sato, H. Shioya, M. Sakaue, T. Iwai, M. Ohfuti, Y. Awano (2005)
Low-resistance multi-walled carbon nanotube vias with parallel channel conduction of inner shells [IC interconnect applications]Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.
-
Tsung-Hao Chen, C. Chen (2001)
Efficient large-scale power grid analysis based on preconditioned Krylov-subspace iterative methodsProceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)
-
Yuan Xie, J. Cong, S. Sapatnekar (2009)
Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures -
N. Srivastava, K. Banerjee (2005)
Performance analysis of carbon nanotube interconnects for VLSI applicationsICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.
-
C. Selvanayagam, J. Lau, Xiaowu Zhang, S. Seah, K. Vaidyanathan, T. Chai (2009)
Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip MicrobumpsIEEE Transactions on Advanced Packaging, 32
-
Young-Joon Lee, Rohan Goel, S. Lim (2009)
Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers
-
C. Cheung, Andrea Kurtz, Hongkun Park, C. Lieber (2002)
Diameter-Controlled Synthesis of Carbon NanotubesJournal of Physical Chemistry B, 106
-
S. Thompson, R. Chau, T. Ghani, K. Mistry, S. Tyagi, M. Bohr (2005)
In search of "Forever," continued transistor scaling one new material at a timeIEEE Transactions on Semiconductor Manufacturing, 18
-
Wei-Shen Kuo, Mingzong Wang, E. Chen, J. Lai, Yu-Po Wang (2008)
Thermal Investigations of 3D FCBGA Packages with TSV Technology2008 3rd International Microsystems, Packaging, Assembly & Circuits Technology Conference
-
Zongwu Tang (2010)
Efficient design practices for thermal management of a TSV based 3D IC system -
S. Borkar (2009)
Design perspectives on 22nm CMOS and beyond2009 46th ACM/IEEE Design Automation Conference
-
Anna Topol, D. Tulipe, L. Shi, S. Alam, D. Frank, S. Steen, J. Vichiconti, D. Posillico, M. Cobb, S. Medd, J. Patel, S. Goma, D. Dimilia, M. Robson, E. Duch, M. Farinelli, C. Wang, R. Conti, D. Canaperi, L. Deligianni, A. Kumar, K. Kwietniak, C. D'Emic, J. Ott, A. Young, K. Guarini, M. Ieong (2005)
Enabling SOI-based assembly technology for three-dimensional (3d) integrated circuits (ICs)IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.
-
P. Garrou, C. Bower, P. Ramm (2012)
Handbook of 3D integration : technology and applications of 3D integrated circuits -
J.H. Wu, J. Alamo (2007)
Through-Substrate Interconnects for 3-D ICs, RF Systems, and MEMS2007 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems
-
Quanlin Liu, Fuxiang Zhang, Takaho Tanaka, T. Aizawa (2002)
Green emission from B2N2CO thin films doped with TbApplied Physics Letters, 81
-
S. Ho, V. Rao, Qratti Khan, S. Yoon, V. Kripesh (2006)
Development of coaxial shield via in silicon carrier for high frequency application2006 8th Electronics Packaging Technology Conference
-
B. Xie, X. Shi, C. Chung, S. Lee (2010)
Novel sequential electro-chemical and thermo-mechanical simulation methodology for annular through-silicon-via (TSV) design2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)
-
M. Bamal, S. List, M. Stucchi, A. Verhulst, M. Hove, R. Cartuyvels, G. Beyer, K. Maex (2006)
Performance Comparison of Interconnect Technology and Architecture Options for Deep Submicron Technology Nodes2006 International Interconnect Technology Conference
-
R. Beica, P. Siblerud, C. Sharbono, M. Bernt (2008)
Advanced Metallization for 3D Integration2008 10th Electronics Packaging Technology Conference
-
M. Mofrad, J. Derakhshandeh, R. Ishihara, A. Baiano, J. Cingel, K. Beenakker (2009)
Stacking of Single-Grain Thin-Film TransistorsJapanese Journal of Applied Physics, 48
-
C. King, Deepak Sekar, M. Bakir, Bing Dang, J. Pikarsky, James Meindl (2008)
3D stacking of chips with electrical and microfluidic I/O interconnects2008 58th Electronic Components and Technology Conference
-
A. Afzali-Kusha, M. Nagata, N. Verghese, D. Allstot (2006)
Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and ValidationProceedings of the IEEE, 94
-
A. Cao, R. Baskaran, M. Frederick, K. Turner, P. Ajayan, G. Ramanath (2003)
Direction‐Selective and Length‐Tunable In‐Plane Growth of Carbon NanotubesAdvanced Materials, 15
-
A. Ural, Yiming Li, H. Dai (2002)
Electric-field-aligned growth of single-walled carbon nanotubes on surfacesApplied Physics Letters, 81
-
M. Rousseau, O. Rozeau, G. Cibrario, G. Carval, M. Jaud, P. Leduc, A. Farcy, Antoine Marty (2008)
Through-silicon via based 3D IC technology: Electrostatic simulations for design methodology -
Nauman Khan, S. Alam, S. Hassoun (2011)
Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) TechnologiesIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19
-
Xin Sun, Ming Ji, Shengli Ma, Yunhui Zhu, Wenping Kang, M. Miao, Yufeng Jin (2010)
Electrical characterization of sidewall insulation layer of TSV2010 11th International Conference on Electronic Packaging Technology & High Density Packaging
-
Peter Singer (2008)
Through-Silicon Vias: Ready for Volume Manufacturing?, 31
-
(2007)
Enabling 3-D design -
W. Davis, John Wilson, S. Mick, Jian Xu, Hao Hua, C. Mineo, A. Sule, M. Steer, P. Franzon (2005)
Demystifying 3D ICs: the pros and cons of going verticalIEEE Design & Test of Computers, 22
-
P. Andry, C. Tsang, E. Sprogis, C. Patel, S. Wright, B. Webb, L. Buchwalter, D. Manzer, R. Horton, R. Polastre, J. Knickerbocker (2006)
A CMOS-compatible process for fabricating electrical through-vias in silicon56th Electronic Components and Technology Conference 2006
-
G. Loh (2008)
3D-Stacked Memory Architectures for Multi-core Processors2008 International Symposium on Computer Architecture
-
P. Jain, T. Kim, J. Keane, C. Kim (2008)
A multi-story power delivery technique for 3D integrated circuitsProceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)
-
M. Gupta, Jarod Oatley, R. Joseph, Gu-Yeon Wei, D. Brooks (2007)
Understanding Voltage Variations in Chip Multiprocessors using a Distributed Power-Delivery Network2007 Design, Automation & Test in Europe Conference & Exhibition
-
S. Ho, S. Yoon, Qiaoer Zhou, K. Pasad, V. Kripesh, J. Lau (2008)
High RF performance TSV silicon carrier for high frequency application2008 58th Electronic Components and Technology Conference
-
F. Kreupl, Andrew Graham, M. Liebau, G. Duesberg, R. Seidel, E. Unger (2002)
Carbon nanotubes for interconnect applicationsIEDM Technical Digest. IEEE International Electron Devices Meeting, 2004.
-
H. Kikuchi, Yusuke Yamada, A. Ali, Jun Liang, T. Fukushima, Tetsu Tanaka, M. Koyanagi (2008)
Tungsten Through-Silicon Via Technology for Three-Dimensional LSIsJapanese Journal of Applied Physics, 47
-
A. Naeemi, Gang Huang, J. Meindl (2007)
Performance Modeling for Carbon Nanotube Interconnects in On-Chip Power Distribution2007 Proceedings 57th Electronic Components and Technology Conference
-
G. Schrom, D. Liu, C. Pichler, C. Svensson, S. Selberherr (1994)
Analysis of Ultra-Low-Power CMOS with Process and Device SimulationESSDERC '94: 24th European Solid State Device Research Conference
-
S. Alam, Robert Jones, S. Rauf, R. Chatterjee (2007)
Inter-Strata Connection Characteristics and Signal Transmission in Three-Dimensional (3D) Integration Technology8th International Symposium on Quality Electronic Design (ISQED'07)
-
Arifur Rahman, J. Trezza, Bernard New, S. Trimberger (2006)
Die Stacking Technology for Terabit Chip-to-Chip CommunicationsIEEE Custom Integrated Circuits Conference 2006
-
Nauman Khan, S. Alam, S. Hassoun (2009)
Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs2009 IEEE International Conference on 3D System Integration
-
J. Chang (2007)
Foundry Future: Challenges in the 21st Century2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
-
J. Burns, B. Aull, C.K. Chen, Chang-Lee Chen, C. Keast, J. Knecht, V. Suntharalingam, K. Warner, P. Wyatt, D. Yost (2006)
A wafer-scale 3-D circuit integration technologyIEEE Transactions on Electron Devices, 53
-
G. Plas, P. Limaye, Igor Loi, A. Mercha, H. Oprins, C. Torregiani, S. Thijs, D. Linten, M. Stucchi, G. Katti, D. Velenis, V. Cherman, B. Vandevelde, V. Simons, I. Wolf, R. Labie, D. Perry, S. Bronckers, N. Minas, Miro Cupac, W. Ruythooren, J. Olmen, A. Phommahaxay, M. Broeck, A. Opdebeeck, M. Rakowski, B. Wachter, M. Dehan, M. Nelis, R. Agarwal, A. Pullini, F. Angiolini, L. Benini, W. Dehaene, Y. Travaly, E. Beyne, P. Marchal (2010)
Design Issues and Considerations for Low-Cost 3-D TSV IC TechnologyIEEE Journal of Solid-State Circuits, 46
-
D. Tezcan, N. Pham, B. Majeed, P. Moor, W. Ruythooren, K. Baert (2007)
Sloped Through Wafer Vias for 3D Wafer Level Packaging2007 Proceedings 57th Electronic Components and Technology Conference
-
B. Goplen, S. Sapatnekar (2006)
Placement of thermal vias in 3-D ICs using various thermal objectivesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25
-
S. Haruehanroengra, Wei Wang (2007)
Analyzing Conductance of Mixed Carbon-Nanotube Bundles for Interconnect ApplicationsIEEE Electron Device Letters, 28
-
Pingqiang Zhou, K. Sridharan, S. Sapatnekar (2009)
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors2009 Asia and South Pacific Design Automation Conference
-
S. Sato, M. Nihei, A. Mimura, A. Kawabata, D. Kondo, H. Shioya, T. Iwai, Miho Mishima, M. Ohfuti, Y. Awano, Fujitsu Limited (2006)
Novel approach to fabricating carbon nanotube via interconnects using size-controlled catalyst nanoparticles2006 International Interconnect Technology Conference
-
R. Tarkiainen, M. Ahlskog, J. Penttila, L. Roschier, P. Hakonen, M. Paalanen, E. Sonin (2001)
Multiwalled carbon nanotube: Luttinger versus fermi liquidPhysical Review B, 64
-
B. Kim, C. Sharbono, T. Ritzdorf, D. Schmauch (2006)
Factors affecting copper filling process within high aspect ratio deep vias for 3D chip stacking56th Electronic Components and Technology Conference 2006
-
D. Brooks, V. Tiwari, M. Martonosi (2000)
Wattch: a framework for architectural-level power analysis and optimizationsProceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201)
- Publisher
- Springer New York
- Copyright
- © The Authors 2013
- ISBN
- 978-1-4614-5507-3
- Pages
- 27 –41
- DOI
- 10.1007/978-1-4614-5508-0_4
- Publisher site
- See Chapter on Publisher Site
Abstract
[Robust power delivery is one of the ITRS scaling grand challenges due to increasing operating frequencies, increasing power density, and decreasing supply voltages. Three dimensional stacking of multiple dies makes this problem even more challenging. In a 3-D IC, only the die adjacent to the package can get power directly from the package. Dies away from the package require new technologies for power delivery. We evaluate in this chapter using TSVs to deliver power in a 3-D IC with the goal of understanding factors that contribute to the performance of a 3-D power delivery network (PDN). We investigate the impact of TSV size. We study various architectural configurations to find the best TSV granularity. We explore the impact of shared and dedicated TSVs on PDN performance and the feasibility of coaxial TSVs for power delivery.]
Published: Aug 27, 2012
Keywords: Power Grid; Functional Block; Silicon Area; Power Delivery; Voltage Droop