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Bias stress effect in low-voltage organic thin-film transistors

Bias stress effect in low-voltage organic thin-film transistors The bias stress effect in pentacene organic thin-film transistors has been investigated. The transistors utilize a thin gate dielectric based on an organic self-assembled monolayer and thus can be operated at low voltages. The bias stress-induced threshold voltage shift has been analyzed for different drain-source voltages. By fitting the time-dependent threshold voltage shift to a stretched exponential function, both the maximum (equilibrium) threshold voltage shift and the time constant of the threshold voltage shift were determined for each drain-source voltage. It was found that both the equilibrium threshold voltage shift and the time constant decrease significantly with increasing drain-source voltage. This suggests that when a drain-source voltage is applied to the transistor during gate bias stress, the tilting of the HOMO and LUMO bands along the channel creates a pathway for the fast release of trapped carriers. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Applied Physics A: Materials Science Processing Springer Journals

Bias stress effect in low-voltage organic thin-film transistors

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References (36)

Publisher
Springer Journals
Copyright
Copyright © 2008 by The Author(s)
Subject
Physics; Condensed Matter Physics; Optical and Electronic Materials; Nanotechnology; Characterization and Evaluation of Materials; Surfaces and Interfaces, Thin Films; Operating Procedures, Materials Treatment
ISSN
0947-8396
eISSN
1432-0630
DOI
10.1007/s00339-008-5019-8
Publisher site
See Article on Publisher Site

Abstract

The bias stress effect in pentacene organic thin-film transistors has been investigated. The transistors utilize a thin gate dielectric based on an organic self-assembled monolayer and thus can be operated at low voltages. The bias stress-induced threshold voltage shift has been analyzed for different drain-source voltages. By fitting the time-dependent threshold voltage shift to a stretched exponential function, both the maximum (equilibrium) threshold voltage shift and the time constant of the threshold voltage shift were determined for each drain-source voltage. It was found that both the equilibrium threshold voltage shift and the time constant decrease significantly with increasing drain-source voltage. This suggests that when a drain-source voltage is applied to the transistor during gate bias stress, the tilting of the HOMO and LUMO bands along the channel creates a pathway for the fast release of trapped carriers.

Journal

Applied Physics A: Materials Science ProcessingSpringer Journals

Published: Dec 19, 2008

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