A CMOS DICE (Dual Interlocked Storage Cell) cell consists of two transistor groups whose layout on the crystal increases the cell’s stability against the impact of single nuclear particles. A fault of the cell’s state does not take place if the particle impacts transistors of one group only. The topological layouts of basic memory elements with a different relative position of two transistor groups of 28 nm CMOS DICE cells were designed and analyzed. Different cell layouts with a distance between the sensitive pairs of transistors of two groups of 1, 2, and 3 µm and a set of basic memory elements for designing memory arrays of static RAM with increased stability with respect to state faults due to the particle track charge separation between two transistor groups of the cell were proposed. The area of the DICE cells is larger by a factor of 2.1–2.5 than that of sixtransistor cells with transistors of the same size.
Russian Microelectronics – Springer Journals
Published: Nov 4, 2015
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