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CHA PT ER 1 1.1 INTRODUCTION For decades, processor systems have benefited from Moore’s Law, doubling clock frequency andtransistordensityeverytwoyears.Siliconperformanceimprovementhasspurrednumerous innovations in designing faster processing systems, with lower data access latency, at a lower cost,everytechnologygeneration.High-performanceprocessorsystemshavereliedonamulti- tiered memory hierarchy for fast data access. The memory tiers closer to the processors provide faster access latency and higher throughput than the tiers farther from the processor. Harddisksandflashmemoriesoccupythelowesttierinthehierarchy.Theyprovidehigh devicedensityatalowerper-bitcost.Traditionalstoragesystemsarecomposedofharddisksor Flash, as they are non-volatile and can retain data across power failures. However, these mass storage technologies have 100x-1000x higher access latency than SRAMs and DRAMs [1–4]. The static random access memories (SRAM) and dynamic random access memories (DRAM) have been traditionally used to build the processor cache hierarchy and main memories. The SRAM-basedcachehierarchyandDRAMsprovidelowerlatencyandhigherthroughputaccess to application data. Unfortunately, the end of Moore’s Law is near [5]; the technology scaling that the semi- conductorindustryhasenjoyedfordecadesiscomingtoanend.Inrecentyears,DRAMtechnol- ogyhasfacedmajorscalabilitychallenges[6,7]andthecostperGBofDRAMhasplateaued[8]. Meanwhile, the demand for DRAM capacity continues to grow, thanks to the surge in high- performancebig-dataapplications[8].Thetwoconflictingtrendshaveresultedinthedaunting memory scalability challenges in data centers. PersistentmemorytechnologiesaimtoofferasolutionforDRAMscalabilitychallenges. Persistent memories (PMs), also known as storage-class memories or non-volatile memories, are denser and consume less power than DRAM. Several technologies, such as Phase Change Memory, Resistive RAM, and Spin Torque Transfer RAM, have been recently explored for
Published: Jan 1, 2022
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