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Lithography-simulation-based design for manufacturability rule development: an integrated circuit design house’s approach

Lithography-simulation-based design for manufacturability rule development: an integrated circuit... We describe design house approaches for design rule developments with emphasis of valuations of pre-optical proximity correction (pre-OPC) layouts and their simulation results. To begin, we describe the procedure of the simulation model calibration. An evaluation of metrics for analyzing the design layouts is then described. Due to the unavailability of post-OPC layouts, both pre-OPC and trial-OPC simulations are studied. A range of layout pattern density, within which the pre-OPC metric follows the post-OPC’s, is estimated. Within this pattern density range, pre-OPC layout then can be evaluated to identify potential process “hot spots.” With this approach, a set of design for manufacturability (DFM) compliance design rules is derived and applied to the product developments for both 90- and 65-nm process technology nodes. Several hot spots in the products (designed with 90-nm design rules) are located and fixed using layout optimization guided by the DFM rules. Simulated image contours and in-line scanning electron microscope (SEM) images validate the approach. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Journal of Micro/Nanolithography, MEMS and MOEMS SPIE

Lithography-simulation-based design for manufacturability rule development: an integrated circuit design house’s approach

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References (17)

Publisher
SPIE
Copyright
Copyright © 2007 Society of Photo-Optical Instrumentation Engineers
ISSN
1932-5150
eISSN
1932-5134
DOI
10.1117/1.2781584
Publisher site
See Article on Publisher Site

Abstract

We describe design house approaches for design rule developments with emphasis of valuations of pre-optical proximity correction (pre-OPC) layouts and their simulation results. To begin, we describe the procedure of the simulation model calibration. An evaluation of metrics for analyzing the design layouts is then described. Due to the unavailability of post-OPC layouts, both pre-OPC and trial-OPC simulations are studied. A range of layout pattern density, within which the pre-OPC metric follows the post-OPC’s, is estimated. Within this pattern density range, pre-OPC layout then can be evaluated to identify potential process “hot spots.” With this approach, a set of design for manufacturability (DFM) compliance design rules is derived and applied to the product developments for both 90- and 65-nm process technology nodes. Several hot spots in the products (designed with 90-nm design rules) are located and fixed using layout optimization guided by the DFM rules. Simulated image contours and in-line scanning electron microscope (SEM) images validate the approach.

Journal

Journal of Micro/Nanolithography, MEMS and MOEMSSPIE

Published: Jul 1, 2007

Keywords: design for manufacture; optical proximity correction; mask error enhancement factor; lithography

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