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International Journal of Navigation and Observation
, Volume 2008 (2008) – May 21, 2008

/lp/hindawi-publishing-corporation/multiple-gate-delay-tracking-structures-for-gnss-signals-and-their-jq0698ZR8N

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- Hindawi Publishing Corporation
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- Copyright © 2008 Heikki Hurskainen et al.
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- 1687-5990
- eISSN
- 1687-6008
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- See Article on Publisher Site

Multiple Gate Delay Tracking Structures for GNSS Signals and Their Evaluation with Simulink, SystemC, and VHDL //// Hindawi Publishing Corporation Home Journals About Us About this Journal Submit a Manuscript Table of Contents Journal Menu Abstracting and Indexing Aims and Scope Article Processing Charges Articles in Press Author Guidelines Bibliographic Information Contact Information Editorial Board Editorial Workflow Free eTOC Alerts Reviewers Acknowledgment Subscription Information Open Focus Issues Focus Issue Guidelines Open Special Issues Published Special Issues Special Issue Guidelines Abstract Full-Text PDF Full-Text HTML Linked References How to Cite this Article Complete Special Issue International Journal of Navigation and Observation Volume 2008 (2008), Article ID 785695, 17 pages doi:10.1155/2008/785695 Research Article <h2>Multiple Gate Delay Tracking Structures for GNSS Signals and Their Evaluation with Simulink, SystemC, and VHDL</h2> Heikki Hurskainen , 1 Elena Simona Lohan , 2 Xuan Hu , 2 Jussi Raasakka , 1 and Jari Nurmi 1 1 Department of Computer Systems, Tampere University of Technology, P.O. Box 553, 33101 Tampere, Finland 2 Department of Communications Engineering, Tampere University of Technology, P.O. Box 553, 33101 Tampere, Finland Received 13 July 2007; Revised 11 December 2007; Accepted 29 February 2008 Academic Editor: Letizia Presti Copyright © 2008 Heikki Hurskainen et al. This is an open access article distributed under the Creative Commons Attribution License , which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Abstract Accurate delay tracking in multipath environments is one of the prerequisites of modern GNSS receivers. Several solutions have been proposed in the literature, both feedback and feedforward. However, this topic is still under active research focus, especially for mass-market receivers, where selection of lowcomplexity, nonpatented methods is preferred. Among the most encountered delay tracking structures implemented in today's receivers, we have the narrow correlator and the double-delta correlators. Both are heavily covered by various patents. The purpose of this paper is to introduce a new, generic structure, called multiple gate delay (MGD) structure, which covers also the patented correlators but offers much more flexibility in the design process. We show how the design parameters of such a structure can be optimized, we argue the performance of this structure via detailed simulation results based on various simulators, such as Matlab/Simulink-based tool, GRANADA, and we test the implementation feasibility of MGD structures on actual devices, via SystemC and FPGA prototyping. One of the main advantages of the proposed structure is its high degree of flexibility, which allows the designer to choose among, to the authors' knowledge, nonpatented solutions with delay tracking accuracy comparable with that of the current state-of-art trackers. 1. Background and Motivation The main algorithms used nowadays for GPS and Galileo code tracking are based on what is typically called a feedback delay estimator, and they are implemented based on a feedback loop. The most known feedback delay estimators are the delay locked loops (DLLs) and the today's GNSS receiver that typically use a particular DLL structure, called the narrow correlator or narrow early-minus-late (NEML) delay tracker, which proved to give good results in multipath environments [ 1 – 3 ]. Another class of enhanced DLL structures is the so-called double-delta correlator class [ 4 ], which started to gain more and more attention during last years. Examples belonging to this class are: the high resolution correlator (HRC) [ 3 , 5 ], the strobe correlator [ 2 , 4 , 6 ], the pulse aperture correlator (PAC) [ 7 ], the multipath mitigation correlator [ 8 ], and the modified correlator reference waveform [ 2 , 9 ]. Most of the double-delta correlators as well as the narrow correlator are patented or under patent applications [ 4 , 5 , 7 , 10 , 11 ]. An alternative to the above-mentioned feedback loop solutions is based on the open-loop (or feedforward) solutions, which refer to the solutions which make the delay estimation in a single step, without requiring a feedback loop. A general classification of open-loop solutions for CDMA communication applications can be found in [ 12 , 13 ] and for GNSS applications in [ 14 ]. However, for the purpose of low-cost mass-market receiver implementation, feedback delay tracking structures are still the preferred ones, and they will be the focus of our paper. We introduce here the flexible multiple gate delay (MGD) structure with adjustable parameters, and we present a method to optimize these parameters. We show the performance of MGD structures in multipath channels, with a particular attention to the situations with more than 2 paths (which are typically neglected in the literature, when analyzing the multipath error envelopes of delay tracking units). We also present, for the first time to the authors' knowledge, a comparison between using squared-envelopes versus envelopes before noncoherent integration stage as well as a comparison between using uniform versus nonuniform gate spacings in delay tracking units. We then validate the MGD structures via implementation in a Simulink-based navigation tool, GRANADA. Based on the presented MGD structures, we also develop a flexible delay tracking prototype receiver (in SystemC and VHDL) for Galileo and GPS signals. The main focus is on sine-BOC and BPSK-modulated signals, but the design steps shown here can be extended in a straightforward manner to other BOC modulations (cosine BOC, multiplexed BOC, alternate BOC, etc.). In the delay tracking receiver prototyping, we focus on the implementability, complexity, and flexibility of the proposed MGD structures. First, we present the implementations and discuss about the flexibility and the restrictions caused mostly by the digital hardware characteristics. Then, we verify the implementability of the chosen algorithms with a SystemC model. After that, the complexity of the implemented prototype hardware is evaluated as VHDL synthesis results. 2. Common Delay Tracking Structures for GNSS Signals The most common delay tracking loops for GNSS signals are based on feedback delay locked loop (DLL)-like structures. The state-of-art delay trackers, which are widely used in GNSS industry nowadays, include: the narrow early-minus-late (NEML) correlator [ 1 – 3 , 10 , 11 ] and the double-delta correlators [ 2 , 15 – 17 ], also known under the names of pulse aperture correlator (PAC) [ 7 ], strobe correlator [ 2 , 6 , 18 ], or high resolution correlator (HRC) [ 3 , 5 , 19 ]. All the above-mentioned methods have a common underlying structure, in the sense that they are based on different weighted combinations of early and late samples of the correlation function with different chip-spacings between these samples. In what follows, we will first introduce the signal model for Galileo and GPS signals, then, we present the above-mentioned methods in more detail. We will then show that most of the currently used delay tracking structures (i.e., those mentioned above) can be unified under a generic structure, namely the multiple gate delay (MGD) structure, whose parameters are to be optimized in Section 3 . Typical satellite positioning signals, such as those used for GPS and Galileo, employ the direct-sequence code division multiple access (DS-CDMA) technique, where a PRN code is spreading the navigation data over 𝑆 𝐹 chips (or over a code epoch length) [ 20 , 21 ]. In what follows, we adopt, for clarity reasons, a baseband model. Also, the delay tracking estimation in nowadays receivers is typically done in digital domain (using the baseband correlation samples). The time notation 𝑡 stands for discrete time. The transmitted signal 𝑥 ( 𝑡 ) can be written as the convolution between the modulating waveform 𝑠 m o d ( 𝑡 ) , the PRN code, including data modulation, and the pulse shaping filter 𝑝 𝑇 𝐵 ( 𝑡 ) [ 22 ]: √ 𝑥 ( 𝑡 ) = 𝐸 𝑏 𝑠 m o d ⊛ ( 𝑡 ) + ∞ 𝑆 𝑛 = − ∞ 𝐹 𝑘 = 1 𝑏 𝑛 𝑐 𝑘 , 𝑛 𝛿 𝑡 − 𝑛 𝑇 s y m − 𝑘 𝑇 𝑐 ⊛ 𝑝 𝑇 𝐵 ( 𝑡 ) , ( 1 ) where 𝐸 𝑏 is the data bit energy, ⊛ is the convolution operator, 𝑏 𝑛 is the 𝑛 th complex data symbol, 𝑇 𝑐 = 1 / 𝑓 𝑐 is the chip period, 𝑆 𝐹 is the spreading factor, 𝑇 s y m is the symbol period ( 𝑇 s y m = 𝑆 𝐹 𝑇 𝑐 ), 𝑐 𝑘 , 𝑛 is the 𝑘 th chip corresponding to the 𝑛 th symbol, 𝛿 ( 𝑡 ) is the Dirac pulse, and 𝑝 𝑇 𝐵 ( 𝑡 ) is the pulse shaping filter applied to pulses of duration 𝑇 𝐵 = 𝑇 𝑐 / 𝑁 𝐵 . Here, 𝑁 𝐵 is a modulation-related parameter that is detailed in what follows. For example, if infinite bandwidth is assumed, 𝑝 𝑇 𝐵 ( 𝑡 ) is a rectangular pulse of unit amplitude if 0 ≤ 𝑡 ≤ 𝑇 𝐵 and 0 otherwise. The signal 𝑥 ( 𝑡 ) is typically transmitted over a multipath static or fading channel, where all interference sources (except the multipaths) are lumped into a single additive Gaussian noise term 𝜂 ( 𝑡 ) : 𝑟 ( 𝑡 ) = 𝐿 𝑙 = 1 𝛼 𝑙 𝑒 − 𝑗 𝜃 𝑙 𝑥 𝑡 − 𝜏 𝑙 𝑒 − 𝑗 2 𝜋 𝑓 𝐷 𝑡 + 𝜂 ( 𝑡 ) , ( 2 ) where 𝑟 ( 𝑡 ) is the received signal, 𝐿 is the number of channel paths, 𝛼 𝑙 is the amplitude coefficient of the 𝑙 th path, 𝜃 𝑙 is the phase of the 𝑙 th path, 𝜏 𝑙 is the channel delay introduced by the 𝑙 th path, 𝑓 𝐷 is the Doppler shift introduced by the channel, and 𝜂 ( 𝑡 ) is the complex additive Gaussian noise of zero mean and double-sided power spectral density 𝑁 0 . Typically, the signal-to-noise ratios for GNSS signals are expressed with respect to the code epoch bandwidth 𝐵 𝑤 , under the name of carrier-to-noise ratio (CNR). The relationship between CNR and bit-energy-to-noise ratio is [ 23 ] 𝐸 C N R [ d B - H z ] = 𝑏 𝑁 0 + 1 0 l o g 1 0 𝐵 𝑤 . ( 3 ) The delay tracking is typically based on the code epoch-by-code epoch correlation ℛ ( ⋅ ) between the incoming signal and the reference 𝑥 r e f ( ⋅ ) modulated PRN code, with a certain candidate Doppler frequency 𝑓 𝐷 and delay ̂ 𝜏 : ℛ 𝑓 ̂ 𝜏 , 𝐷 1 , 𝑚 = 𝐄 𝑇 s y m 𝑚 𝑇 s y m ( 𝑚 − 1 ) 𝑇 s y m 𝑟 ( 𝑡 ) 𝑥 r e f 𝑓 ̂ 𝜏 , 𝐷 𝑑 𝑡 , ( 4 ) where 𝑚 is the code epoch index, and 𝐄 ( ⋅ ) is the expectation operation, with respect to the PRN code, and 𝑥 r e f 𝑓 ̂ 𝜏 , 𝐷 = ( 𝑠 m o d ( 𝑡 ) ⊛ + ∞ 𝑆 𝑛 = − ∞ 𝐹 𝑘 = 1 ̂ 𝑏 𝑛 𝑐 𝑘 , 𝑛 𝛿 𝑡 − 𝑛 𝑇 s y m − 𝑘 𝑇 𝑐 ⊛ 𝑝 𝑇 𝐵 ( 𝑡 ) ) × 𝑒 + 𝑗 2 𝜋 𝑓 𝐷 𝑡 , ( 5 ) where ̂ 𝑏 𝑛 are the estimated data bits. For Galileo signals, a separate pilot channel is transmitted, thus the data bits are known at the receiver [ 21 ]. In order to reduce the noise level, we can use coherent and/or noncoherent integration. The averaged coherent correlation function ℛ 𝑐 𝑓 ( ̂ 𝜏 , 𝐷 ) can be written as ℛ 𝑐 𝑓 ̂ 𝜏 , 𝐷 = 1 𝑁 𝑐 𝑁 𝑐 𝑚 = 1 ℛ 𝑓 ̂ 𝜏 , 𝐷 , 𝑚 , ( 6 ) where 𝑁 𝑐 is the coherent integration time (expressed in code epochs or milliseconds for GPS/Galileo signals), and the averaged noncoherent correlation function ℛ 𝑛 𝑐 𝑓 ( ̂ 𝜏 , 𝐷 ) can be written as ℛ 𝑛 𝑐 𝑓 ̂ 𝜏 , 𝐷 = 1 𝑁 𝑛 𝑐 𝑁 𝑛 𝑐 | 1 𝑁 𝑐 𝑁 𝑐 𝑚 = 1 ℛ 𝑓 ̂ 𝜏 , 𝐷 | , 𝑚 p o w 𝑛 𝑐 , ( 7 ) where 𝑁 𝑛 𝑐 is the noncoherent integration time, expressed in blocks of length 𝑁 𝑐 milliseconds (for clarity of presentation, we dropped the block indexes used in the noncoherent summation), and p o w 𝑛 𝑐 is a power index used for noncoherent summation. The most encountered variants are: p o w 𝑛 𝑐 = 1 (i.e., sum of absolute values) and p o w 𝑛 𝑐 = 2 (i.e., sum of squared-absolute values). The DLL-like structures form a discriminator function 𝐷 ( ̂ 𝜏 ) based on the early and late correlations, and they estimate the channel first path delay from the zero crossings of this discriminator function. The discriminator functions for NEML [ 1 – 3 , 10 , 11 ] and HRC [ 3 , 5 , 19 ] are well defined in literature and their expressions as equations are, for NEML: 𝐷 ( ̂ 𝜏 ) = ℛ 𝑐 / 𝑛 𝑐 Δ ̂ 𝜏 + 1 2 , 𝑓 𝐷 − ℛ 𝑐 / 𝑛 𝑐 Δ ̂ 𝜏 − 1 2 , 𝑓 𝐷 , ( 8 ) and for HRC: 𝐷 ( ̂ 𝜏 ) = 𝑎 1 ℛ 𝑐 / 𝑛 𝑐 Δ ̂ 𝜏 + 1 2 , 𝑓 𝐷 − ℛ 𝑐 / 𝑛 𝑐 Δ ̂ 𝜏 − 1 2 , 𝑓 𝐷 + 𝑎 2 ℛ 𝑐 / 𝑛 𝑐 Δ ̂ 𝜏 + 2 2 , 𝑓 𝐷 − ℛ 𝑐 / 𝑛 𝑐 Δ ̂ 𝜏 − 2 2 , 𝑓 𝐷 . ( 9 ) In single-path channels ( 𝐿 = 1 ), the mentioned discriminator functions cross the zero level when ̂ 𝜏 = 𝜏 1 . That is, the zero-crossings show the presence of a channel path. However, due to BOC modulation, we might have more zero-crossings present, and the search range should be restricted to the linear range of the discriminator function (for SinBOC(1,1)), this linear range goes from about −0.05 till about 0.05 chip error. In multipath channels, we also want to have 𝐷 ( 𝜏 1 ) = 0 , 𝜏 1 being the true line-of-sight (LOS) delay, in order to estimate correctly the first path delay. However, this is not always possible, and an estimation error might happen due to multipath presence, that is, 𝐷 ( 𝜏 1 + 𝑒 m e ) = 0 . The term 𝑒 m e is the multipath error. An example is shown in Figure 1 for two in-phase paths of amplitudes 0 and −1 dB and path spacing of 0.2 chips. In this example, 𝑒 m e = 0 . 0 1 chips for HRC, and 𝑒 m e = 0 . 0 4 chips for NEML (in single-path channel, we had 𝑒 m e = 0 chips for both structures). The maximum and minimum multipath errors define the multipath error envelopes (MEEs), as it will be discussed in more detail in Section 3 . Figure 1: Examples of noncoherent discriminator outputs ( p o w 𝑛 𝑐 = 2 ) for two-path channels, for NEML and HRC correlators. SinBOC(1,1) signal, early-late spacing Δ 1 = 0 . 1 chips. While it is generally known that the performance of coherent correlators outperforms that of the noncoherent correlators in ideal conditions (e.g., absence of fading or clock synchronization errors, perfect data bit estimation, etc.), the nonidealities of practical channels make that the structures of choice in most nowadays receivers are the noncoherent ones. This motivates our choice of noncoherent correlator gates in what follows. 3. Multiple Gate Delay (MGD) Structures 3.1. Proposed Architecture The proposed generalization of the NEML and double-delta structures (which cover most of the state-of-art delay tracking techniques used nowadays in industrial implementations) follows in a straightforward manner: 𝐷 ( ̂ 𝜏 ) = 𝑁 𝑔 𝑖 = 1 𝑎 𝑖 ℛ 𝑐 / 𝑛 𝑐 Δ ̂ 𝜏 + 𝑖 2 , 𝑓 𝐷 − ℛ 𝑐 / 𝑛 𝑐 Δ ̂ 𝜏 − 𝑖 2 , 𝑓 𝐷 . ( 1 0 ) Above, we have a weighted sum of 𝑁 𝑔 correlation pairs (or gates), with weighting factors 𝑎 𝑖 , 𝑖 = 1 , … , 𝑁 𝑔 , and spacings between the 𝑖 th early and the 𝑖 th late gate equal to Δ 𝑖 . Uniform spacing between the gates (as that one used in NEML and double-delta correlators) means that Δ 𝑖 = 𝑖 Δ 1 , 𝑖 = 2 , … , 𝑁 𝑔 . However, we need not to restrict our structure to uniform spacing alone. The above discriminator function characterizes the proposed multiple gate delays (MGDs). The first coefficient 𝑎 1 is normalized, in what follows, to 1 without loss of generality. An example of the discriminator function for MGD with uniform and nonuniform spacings is shown in Figure 2 . For 2-path channel, the same channel profile as in Figure 1 was used. The multipath errors in these cases are: 𝑒 m e = − 0 . 0 0 2 5 chips for MGD with uniform spacing and 𝑒 m e = 0 . 0 1 5 0 chips for MGD with nonuniform spacing. Figure 2: Examples of noncoherent discriminator outputs ( p o w 𝑛 𝑐 = 2 ) for single-path and two-path channels, for 2 types of MGD correlators, each with 𝑁 𝑔 = 2 gate pairs: uniform spacing ( Δ 2 = 2 Δ 1 ) versus decreasing spacing ( Δ 2 = 1 . 5 Δ 1 ). SinBOC(1,1) signal, early-late spacing Δ 1 = 0 . 1 chips. 𝑎 1 = 1 for both structures. The block diagram of the generic MGD structures is shown in Figure 3 . The incoming signal is correlated with the reference, BOC or BPSK-modulated PRN code, via 𝑁 𝑔 gates or correlator pairs, and, then, it is coherently and noncoherently integrated. The coherent and noncoherent integration blocks are optional, but they usually should be employed for a better robustness against noise. The type of nonlinearity that can be used in the implementation is determined by the factor p o w 𝑛 𝑐 , with typical values: p o w 𝑛 𝑐 = 1 (envelope) or p o w 𝑛 𝑐 = 2 (squared envelope). The choice of nonlinearity type is usually motivated by the design constraints (e.g., complexity of squaring versus taking absolute value, possible need for analytical models, which are easier to derive in the case of squared envelopes, via chi-squared statistics, etc.), therefore we will analyze both cases ( p o w 𝑛 𝑐 = 1 , 2 ) in what follows. To the authors' knowledge, a comparison between squared envelopes and envelopes used in noncoherent integration is not yet available in the GNSS literature. Figure 3: Block diagram of MGD delay tracking structures. We remark that the structure shown in Figure 3 is not the only one possible; we might, in fact, combine the early-late gates after the discriminator function. Such structures have been analyzed in [ 24 ] and were shown to give worse results than the MGD structure selected here. We also notice that the term of MGD has been used before in [ 15 , 16 ]. We kept the same MGD nomination, since it is quite a generic one, but, by difference with our proposed MGDs, the discriminator formed in [ 15 , 16 ] is a normalized discriminator, and the choice of the weighting parameters is not optimized. It is not surprising then, that, while getting rid of the false lock point problem, the MGD structures proposed in [ 15 , 16 ] have even poorer code tracking performance than the narrow correlator [ 16 ]. We also remark that the linear combination of weighted correlation in order to shape the discriminator function has been also considered in [ 25 ]. There, the coefficients are optimized reducing the value of the correlation function outside the region ± 1 chip therefore consequently reducing the multipath error envelope area. However, the approach presented in [ 25 ] has been tested only for 2-path channels, with second path weaker than LOS path, and the optimization steps for other multipath scenarios seem to depend on previous knowledge about multipath profiles, which is not usually available. Our approach is different in the sense that we do not try to reach an optimal discriminator shape, but the optimization is done according to the estimated multipath errors, in such a way to minimize them, on average (i.e., under the assumption of various statistical distributions of channel paths, this optimization is performed, and the MGD parameters are found). The next step is to choose the MGD parameters, namely the number of gating pairs 𝑁 𝑔 , the weighting coefficients 𝑎 𝑖 , and the gate spacings Δ 𝑖 . This choice is done according to an optimization criterion defined in the presence of multipath channels, as given in Section 3.2 . 3.2. Optimization Criterion The typical criterion to evaluate the performance of a delay tracking unit in the presence of multipaths is the multipath error envelope (MEE) [ 1 ]. Typically, two paths, either in-phase or out-of-phase, are assumed to be present, and the multipath error is computed versus the path spacing. The upper error envelope is obtained when the paths are in-phase and the lower error envelope when the paths have 180 ° phase difference. The MEEs depend on the type and length of the PRN codes, on the additive white Gaussian noise (AWGN) level, and on the residual Doppler shift errors coming from the acquisition stage. However, in order to distinguish the performance deterioration due to multipath errors only, several simplifying assumptions can be made, such as: zero AWGN, ideal infinite-length PRN codes, and zero residual Doppler ( 𝑓 𝐷 = 𝑓 𝐷 ). Under these assumptions, after straightforward manipulations of ( 1 ), ( 2 ), ( 4 ), ( 5 ), ( 6 ), and ( 7 ), for noncoherent integration we obtain the following: ℛ 𝑛 𝑐 𝑓 ̂ 𝜏 , 𝐷 √ = | 𝐸 𝑏 𝐿 𝑙 = 1 𝛼 𝑙 𝑒 − 𝑗 𝜃 𝑙 ℛ m o d ̂ 𝜏 − 𝜏 𝑙 | p o w 𝑛 𝑐 , ( 1 1 ) where ℛ m o d ( 𝜏 ) is the autocorrelation function of the modulated PRN code, given by [ 22 ] ℛ m o d ( 𝜏 ) = Λ 𝑇 𝐵 ( 𝑡 ) ⊛ 𝑁 𝐵 2 − 1 𝑁 𝑘 = 0 𝐵 2 − 1 𝑘 1 𝑁 = 0 𝐵 1 − 1 𝑁 𝑖 = 0 𝐵 1 − 1 𝑖 1 = 0 ( − 1 ) 𝑘 + 𝑘 1 + 𝑖 + 𝑖 1 × 𝛿 𝑡 − 𝑖 𝑇 𝐵 1 + 𝑖 1 𝑇 𝐵 1 − 𝑘 𝑇 𝐵 + 𝑘 1 𝑇 𝐵 , ( 1 2 ) where Λ 𝑇 𝐵 ( 𝑡 ) = 𝑝 𝑇 𝐵 ⊛ 𝑝 𝑇 𝐵 is the triangular pulse of support 2 𝑇 𝐵 , shown in Figure 4 . Figure 4: Illustration of a triangular pulse Λ 𝑇 𝐵 ( 𝑡 ) of support 2 𝑇 𝐵 . The MEEs can be then computed straightforwardly, under these ideal conditions, from ( 10 ), ( 11 ), and ( 12 ) (noncoherent structures), by considering two-paths in-phase and out-of-phase channels. However, since the multipath profiles cannot be known in advance, we can compute some averaged MEEs, when the second-path amplitude varies. The approach selected by us was to consider that the first channel path has a unit amplitude, and the second-path amplitude varies uniformly between 0.3 and 1.0. The final MEEs will be obtained as an average of all MEEs for each channel profile. A good delay tracking structure should furnish small average errors, small worst errors, and small maximum multipath spacing after which MEE becomes 0. The proposed optimization criterion, derived by intuitive reasoning is the area enclosed by the absolute value of the upper MEE and the absolute value with minus sign of the lower MEE. The illustration of this “enclosed area” principle is shown in Figure 5 for a MGD structure with 3 gate pairs, squared absolute value ( p o w 𝑛 𝑐 = 2 ), and delta spacings and weighting coefficients shown in the figure's caption. The “enclosed area” is shown in dashed lines. We remark that the units to measure this area are the units of MEEs (e.g., chips or meters); here the errors are shown in meters, knowing that one chip error corresponds to 293.25 m (if the chip rate is 1.023 MHz). Figure 5: Illustration of the “enclosed area” principle for 2 path channel. Noncoherent MGD structure with p o w 𝑛 𝑐 = 2 , 𝑁 𝑔 = 3 , 𝑎 1 = 1 , 𝑎 2 = − 0 . 7 , 𝑎 3 = 0 . 1 , and Δ 1 = 0 . 1 chips, Δ 2 = 0 . 2 chips, Δ 3 = 0 . 3 chips. 3.3. Tables with Optimized Parameters and Interpretation of Results As mentioned before, the parameters to be optimized are: the number of gate pairs 𝑁 𝑔 , the delta (or early-late) spacings Δ 𝑖 , the weighting coefficients 𝑎 = { 𝑎 𝑖 } 𝑖 = 1 , … , 𝑁 𝑔 , and the type of nonlinearity p o w 𝑛 𝑐 . Three types of delta spacings have been studied here. (1) Uniform spacing: Δ 𝑖 = 𝑖 Δ 1 , 𝑖 = 2 , … , 𝑁 𝑔 . (2) Decreasing spacing: Δ 𝑖 = ( ( 2 𝑖 − 1 ) / 2 𝑖 − 1 ) Δ 1 , 𝑖 = 2 , … , 𝑁 𝑔 . (3) Increasing spacing: Δ 𝑖 = ( ( 2 𝑖 + 1 ) / 2 ) Δ 1 , 𝑖 = 2 , … , 𝑁 𝑔 . The target was to minimize the area enclosed by the averaged MEEs, when the amplitude of the second channel path varied between 0.3 and 1.0 (linear scale), and the multipath spacing varied between 0 and 1.5 chips (with a step of 0.01). For convenience and without loss of generality, we normalized the weighting coefficients with respect to the first one. Thus, 𝑎 1 = 1 , and the search ranges for 𝑎 𝑖 were between −1 and +1, with a step of 0.1. First, we had a look at the minimum enclosed areas for 𝑁 𝑔 = 2 and 𝑁 𝑔 = 3 (in order to see the effect of increasing the number of gating pairs), and for the two types of nonlinearities p o w 𝑛 𝑐 = 1 and p o w 𝑛 𝑐 = 2 . For SinBOC(1,1) modulation, the minimum enclosed areas are shown in Tables 1 and 2 , and they correspond to the optimum coefficients given (partly) in Table 3 (only the most illustrative cases, i.e., uniform and decreasing spacings, are shown in this last referenced table). Table 1: Minimum enclosed areas [chips] (i.e., for optimum coefficient pairs), 𝑁 𝑔 = 2 , SinBOC(1,1) signal. Minimum early-late spacing Δ 1 is given in chips. Table 2: Minimum enclosed areas [chips] (i.e., for optimum coefficient pairs), 𝑁 𝑔 = 3 , SinBOC(1,1) signal. Minimum early-late spacing Δ 1 is given in chips. Table 3: Optimum coefficient pairs 𝑎 𝑖 . 𝑁 𝑔 = 3 . SinBOC(1,1) signal (Galileo). Minimum early-late spacing Δ 1 is given in chips. Two well-known reference structures are also shown here for comparison purposes: the narrow correlator NEML and the high resolution correlator (HRC), both with p o w 𝑛 𝑐 = 1 (which proved better than p o w 𝑛 𝑐 = 2 ). In fact, both these structures are particular cases of the proposed MGDs: NEML has 𝑎 = [ 1 , 0 , 0 ] , as shown in ( 8 ), HRC has 𝑎 = [ 1 , − 0 . 5 , 0 ] , and Δ 2 = 2 Δ 1 (uniform spacing), according to ( 9 ). If we compare Table 1 ( 𝑁 𝑔 = 2 ) with Table 2 ( 𝑁 𝑔 = 3 ), we remark that, by increasing the number of gate pairs, we may decrease the enclosed MEE area, and, thus, we may increase the multipath robustness. In the worst case, the areas remain the same when going from 𝑁 𝑔 = 2 to 𝑁 𝑔 = 3 gate pairs, which means that the optimum is already achieved with a double-delta correlator-like structure. In this situation, the optimum is typically given by HRC (see the last column of Tables 1 and 2 ). We also remark that the reduction of the enclosed area is not very large when we increase the number of gate pairs, which might justify the fact that we limit our structures to a maximum of 𝑁 𝑔 = 3 gate pairs (further increase in the number of gate pairs will boost the complexity, while providing only marginal benefit in terms of robustness against multipaths). It is also seen from Tables 1 and 2 that using envelopes ( p o w 𝑛 𝑐 = 1 ) instead of squaring envelopes ( p o w 𝑛 𝑐 = 2 ) gives better results. Also, using a decreasing delta spacing instead of uniform delta spacing is generally better. Similar conclusions have been achieved also for GPS BPSK-modulated signals. The optimum pairs of coefficients for the two nonlinearity types are shown in Table 3 , for SinBOC(1,1) modulation, and in Table 4 for BPSK modulation. Only uniform and decreasing delta spacings are considered here, since the increasing delta spacing was clearly much worse than the other two types of spacing (as seen in Tables 1 and 2 ). Table 4: Optimum coefficient pairs 𝑎 𝑖 . 𝑁 𝑔 = 3 . BPSK signal (GPS). Minimum early-late spacing Δ 1 is given in chips. An illustration of the averaged MEEs for the narrow correlator, high resolution correlator, MGD with uniform spacing ( 𝑎 1 = 1 , 𝑎 2 = − 0 . 7 , 𝑎 3 = − 0 . 2 ), and MGD with decreasing spacing ( 𝑎 1 = 1 , 𝑎 2 = − 0 . 9 , 𝑎 3 = 0 . 2 ) is shown in Figure 6 , for SinBOC(1,1) signal, envelope-based nonlinearity ( p o w 𝑛 𝑐 = 1 ), and 0.25 chips minimum early-late spacing. The average is done with respect to the second channel path amplitude, which varies uniformly between 0.3 and 1.0 (when first channel path has unit amplitude). As discussed before, the best results among these 4 algorithms are obtained with the decreasing spacing, but the differences between the 4 considered tracking structures are not very large. Figure 6: Illustration of the averaged MEEs for NEML, HRC, and two MGDs with optimal parameters as given in Table 3 (for uniform and decreasing spacings). p o w 𝑛 𝑐 = 1 , Δ 1 = 0 . 2 5 chips, and SinBOC(1,1) signals. The values shown in Tables 3 and 4 give the designer the possibility of a wide choice of MGD parameters, according to the desired nonlinearity type (imposed, for example, by hardware restrictions) and to the desired minimum early-late spacing Δ 1 . As seen in Tables 1 and 2 , the smaller the minimum early-late spacing, the better the multipath performance. However, as mentioned in [ 23 ], the delay tracking error decreases with the early-late spacing only if we assume infinite bandwidth. If the bandwidth is limited, there is a lower bound limit on the minimum early-late spacing. Although closed form expressions for this limit do not exist, a coarse limitation of the order of Δ 1 = 1 / 𝐵 𝑟 𝑥 has been derived in [ 26 ], where 𝐵 𝑟 𝑥 is the receiver front-end bandwidth. For example, if the receiver bandwidth is limited to 20 MHz, the minimum early-late spacing that we can use will be around Δ 1 = 0 . 0 5 chips. Decreasing the early-late spacing below this limit will not provide any additional benefit in terms of code tracking error, it will only decrease the linear range of the discriminator. A large linear range of the discriminator curve is also important, since it is directly related to the ability of the loop to keep the lock. The linear range is directly proportional with half of the early-late spacing Δ 1 / 2 , as illustrated in Figure 7 (there, the linear range for Δ 1 = 0 . 1 chips goes from −0.05 till 0.05 chips, and the linear range for Δ 1 = 0 . 3 chips goes from −0.1 till 0.1 chips, with high likelihood that the loop will not lose lock as long as the error is below 0.15 chips in absolute value, due to the piece-wise linear and monotonic shape of the discriminator in the region −0.15 to 0.15 chips). An approximation of the linear range of the discriminator is therefore given by Δ 1 / 2 . Thus, when choosing Δ 1 , the designer should take into account the multipath performance, on one hand, and the bandwidth limitations and linear range constraints, on the other hand. Figure 7: Illustration of the linear range of the discriminator, when we increase the minimum early-late spacing. MGDs with 𝑁 𝑔 = 3 , decreasing spacings, p o w 𝑛 𝑐 = 1 , and optimal parameters as given in Table 3 . 3.4. Mees for More Than 2 Paths When we want to analyze the MEEs in channels with more than 2 paths, there are no analytical expressions to compute them, due to the complexity of channel interactions. Thus, we cannot know if the “worst” case errors happen when all the paths are in phase or when they have alternate phases, and so forth. The solution we propose here in order to compute MEEs for multiple-paths channels is based on Monte-Carlo simulations: we generate a sufficient number of random channel realizations 𝑁 r a n d o m , and we look at the highest positive and negative multipath errors over the 𝑁 r a n d o m points. The goal is to study the MGD performance in multipath channels with more than 2 channel paths (which may occur especially in and urban indoor scenarios). For this purpose, we consider that the channel impulse response ℎ ( 𝑡 ) is given by (same notations from ( 2 ) are used here) ℎ ( 𝑡 ) = 𝐿 𝑙 = 1 𝛼 𝑙 𝑒 − 𝑗 𝜃 𝑙 𝛿 𝑡 − 𝜏 𝑙 . ( 1 3 ) We made the following assumptions during the following simulations: that the channel has a decaying power delay profile (PDP), meaning that 𝛼 𝑙 = 𝛼 1 𝑒 − 𝜇 ( 𝜏 𝑙 − 𝜏 1 ) , where 𝜇 is the PDP coefficient (assumed in the simulations to be uniformly distributed in the interval [0.5; 1] when the path delays are expressed in samples), that the channel path phases 𝜃 𝑙 are uniformly distributed in the interval [0; 2 π ], that the number of channel paths 𝐿 is uniformly distributed between 2 and 𝐿 m a x (with 𝐿 m a x = 3 , 4 , … , 𝑛 ), and that the successive path spacing 𝜏 𝑙 − 𝜏 𝑙 − 1 is uniformly distributed in the interval [ 1 / 𝑁 𝑠 𝑁 𝐵 ; 𝑥 m a x ] , where 𝑁 𝑠 is the oversampling factor or number of samples per BOC interval (a parameter which defines the resolution of the delay estimates), and 𝑥 m a x is the maximum value of the successive path spacing (which will define the multipath delay axis in the MEE curves). It follows that, for each channel realization (meaning a combination of amplitudes 𝛼 = 𝛼 1 , … , 𝛼 𝐿 , phases 𝜃 = 𝜃 1 , … , 𝜃 𝐿 , path spacings, and number of channel paths 𝐿 ), a certain LOS delay is estimated ̂ 𝜏 1 ( 𝛼 , 𝜃 , 𝐿 ) from the zero crossing of the discriminator function ( 𝐷 ( 𝜏 ) | ̂ 𝜏 1 ( 𝛼 , 𝜃 , 𝐿 ) = 0 ) , searched in the linear region of 𝐷 ( ⋅ ) . The LOS estimation error is thus ̂ 𝜏 1 ( 𝛼 , 𝜃 , 𝐿 ) − 𝜏 1 , where 𝜏 1 is the true LOS path delay. The multipath error envelopes (upper and lower) for a particular path spacing 𝑥 m a x can be therefore computed as M E E u p p e r 𝑥 m a x = m a x 𝛼 , 𝜃 , 𝐿 ̂ 𝜏 1 ( 𝛼 , 𝜃 , 𝐿 ) − 𝜏 1 , M E E l o w e r 𝑥 m a x = m i n 𝛼 , 𝜃 , 𝐿 ̂ 𝜏 1 ( 𝛼 , 𝜃 , 𝐿 ) − 𝜏 1 . ( 1 4 ) The results based on the above rule are shown in Figure 8 for 𝐿 m a x = 6 maximum channel paths. Similar results have been achieved also for 𝐿 m a x between 3 and 5 paths, with the only difference that the MEE levels are increasing when the number of path increases (this can be noticed also if we compare Figure 8 with Figure 6 ). Several structures with optimized parameters as given in Table 3 and different nonlinearity types were used here. The surprising result is that the higher the number of channel paths is, the more the performance of various MGD structures becomes similar for all the considered algorithms (and they all reach the performance of the narrow correlator). It follows that the main advantage of the proposed MGD structures comes from the fact that they offer patent-free alternatives to the current narrow and double-delta correlators, by preserving the same performance in realistic multipath channels. Figure 8: Multipath error envelopes for channels with more than 2 paths ( 𝐿 m a x = 6 paths), minimum early-late spacing Δ 1 = 0 . 2 5 chips, SinBOC(1,1) signal. 4. Simulink/Granada-Based Implementation 4.1. Model Description The Galileo receiver analysis and design application (GRANADA), developed by Deimos Space within GARDA project, is one of the popular GNSS simulation tools nowadays. It consists of two parts: Bit-true GNSS SW receiver simulator and GNSS Environment and Navigation simulator. Since the Bit-true GNSS SW receiver simulator is created based on the Simulink/Matlab, it is easy to be modified for new receiver technologies. This simulator is currently used by several universities and researchers [ 16 , 27 – 29 ]. The GRANADA Bit-true GNSS SW receiver simulator is made up by three parts: the transmitter block, the propagation channel block, and receiver block, as shown in Figure 9 . The transmitter block includes the code generation, BOC modulation, and channel multiplexing. The propagation channel model takes into consideration the multipaths, the AWGN noise, and a few other possible sources of interference, such as the wideband interference from other satellites. The receiver block contains basically receiver front end, acquisition, and code tracking blocks. The general architecture of receiver is shown in Figure 10 . After some modification in GRANADA version 2.02, which is distributed under Galileo supervisory authority (GSA) licenses, it can be used for testing the performance of MGD structure. The modifications made to GRANADA tool are explained with details in [ 29 , 30 ]. Figure 9: The basic diagram of GRANADA Bit-true software receiver simulator. Figure 10: The simplified baseband receiver diagram in GRANADA (NEML). 4.2. Results in Awgn and Multipath Static and Fading Channels In order to evaluate the performance of the new structures, root mean square error (RMSE) between the estimated delay and the true LOS delay is calculated. In order to test the DLL performance in the noise presence, we chose three kinds of channel profiles: single-path static channel, two-path static channel, and four-path fading channel, as shown in Table 5 . Table 5: Simulation scenarios for Simulink/GRANADA-based simulations. Figures 11 , 12 , and 13 show the RMSE values of different algorithms in the different channel settings. Since the received signal cannot get synchronized in the acquisition stage of GRANADA when CNR is below 35 dB-Hz, we calculate the RMSE values from 35 dB-Hz to 50 dB-Hz. Structures with early-late spacing Δ 1 = 0 . 1 chips have been selected for comparison purpose, but similar results (which are in accordance with the models given in Section 3 ) were obtained for other early-late spacings as well. Figure 11: The RMSE simulation results in single-path static channel, Δ 1 = 0 . 1 chips, p o w 𝑛 𝑐 = 2 . Figure 12: The RMSE simulation results in two-path static channel, Δ 1 = 0 . 1 chips, p o w 𝑛 𝑐 = 2 . Figure 13: RMSE simulation results in 4-path fading channel, Δ 1 = 0 . 1 chips, p o w 𝑛 𝑐 = 2 . Besides the MGD structures described in Section 3 , we also considered here a normalized MGD structure, where the discriminator function is normalized by the weighted sum of early and late correlations, similar with [ 15 , 16 ]: 𝐷 n o r m = ( ̂ 𝜏 ) 𝐷 ( ̂ 𝜏 ) ∑ 𝑁 𝑔 𝑖 = 1 𝑎 𝑖 ℛ 𝑐 / 𝑛 𝑐 ̂ 𝜏 + Δ 𝑖 𝑓 / 2 , 𝐷 + ℛ 𝑐 / 𝑛 𝑐 ̂ 𝜏 − Δ 𝑖 𝑓 / 2 , 𝐷 . ( 1 5 ) The purpose of including the normalized MGD in the comparison was to show that the normalized MGD structures of [ 15 , 16 ] have worse performance than the un-normalized structures proposed by us. The delay error between the initial code replica in the receiver and the received signal has not been taken into account. The estimated delay values used for calculating RMSE are taken after the transient stage in the beginning of the tracking stage. From Figures 11 and 12 , the simulation results in the static channel show that as CNR increases, the estimation delay errors converge to the corresponding value in the MEEs. For scenario 1, the estimated delay errors are caused by the noise only, since there is only LOS signal in the propagation channel. As the CNR increases, the RMSE value of each algorithm gets close to 0. When CNR is equal to 50 dB-Hz, the RMSE values are below 0.5 meters. From the single path simulation results, we notice that all these algorithms have similar performance in the AWGN channel, as desired. For scenario 2, as the CNR increases, the RMSE value of each algorithm converge to different values. This is because the RMSE value takes both bias and variance into account. The variance is caused by the noise and decreases when CNR increases. However, the bias is caused by the multipath in the channel and is equal to the corresponding point in the MEEs. For instance, as the CNR increases, the RMSE values of NEML algorithm converge to 11 meters, which is the same value in the MEEs according to the channel profile of scenario 2. The normalized MGD has worse behavior than an un-normalized MGD with the same parameters. From Figure 12 , it is clear that the HRC algorithm and MGD algorithm with weighting factors 𝑎 = ( 1 , − 0 . 6 , 0 ) show better performance than NEML algorithm, and MGD algorithm with 𝑎 = ( 1 , − 0 . 7 , 0 . 1 ) (i.e., optimum parameters) shows the best performance among all considered algorithms (which is in accordance with the theoretical derivations in Section 3.2 ). In the multipath fading channel, the LOS signal follows Rician distribution, and the NLOS signals follow Rayleigh distribution. The mean power and delay of each ray are described in Table 5 . Figure 13 shows that the RMSE value of NEML is much higher than other algorithms, especially when CNR is 35 dB-Hz, it gets till 1 7 2 meters (not shown in the figure in order to get a better scale). An MGD structure with weighting factor 𝑎 = ( 1 , − 0 . 7 , 0 . 1 ) shows again the best performance among the algorithms, as expected, according to the optimization results given in Section 3 . The RMSE performance of normalized MGD algorithm is quite poor in fading channels. 5. Algorithm Testing/Prototyping From the MGD structure optimization results (Tables 2 and 3 ), we chose the MGD algorithm with 𝑁 𝑔 = 3 to be investigated further in prototype stage. Both uniform and decreasing spacings with the Δ 1 = 0 . 1 and Δ 1 = 0 . 2 5 chips were chosen to be studied. The purpose here is to show that the chosen tracking algorithms are feasible to be implemented on actual devices. One of the targets of this study was to see if the behavior of the proposed algorithms does change due to the restrictions given by the hardware implementation. These restrictions include finite computation accuracy, and the effect of quantization due to the bit-width of the signals and the limitation caused by the operation frequency of the synchronous digital system. We also focus on the design complexity issue, which characterizes the algorithm development especially in the low cost receivers. Since the trend in price of the satellite navigation receivers is currently descending [ 31 ], the manufacturers of these low cost, mass market, receivers will most likely reject the algorithms with high implementation complexity and cost. In the satellite navigation receiver, the signal tracking is performed by hardware and software signal processing [ 23 ]. On the evolving field of satellite navigation systems, the issue of flexility has become more and more important. Flexible designs allow algorithm updates if the specifications of upcoming systems (like Galileo) change suddenly. Flexible designs are usually relying on software-based implementation [ 32 ]. For receivers, the software-based implementation is declared to be minimizing the area and cost. On the other hand, the computation burden of the real-time tracking algorithms is too high for most of the handheld device processors, and thus hardware-based computation acceleration is also required. The division between hardware and software implementation may vary in different cases and from the cost perspective it has quite an important role. For this software versus hardware division, one approach in the literature has been the division where the correlation of incoming signal and the reference code are implemented as a specific hardware accelerator, and the computation of discriminators for the feedback loop is done by software running on a digital signal processor (DSP) or some specific processor [ 20 , 33 ]. In the commercial receiver chip sets, this division is usually implemented as a specific hardware GPS accelerator, engine or core, which is connected to an embedded processor [ 34 , 35 ]. We chose this approach with the focus on the hardware complexity for our algorithm prototyping implementation. We used the hardware synthesis results (i.e., resource consumption on target FPGA) to estimate the relative complexity of the implemented algorithms. 5.1. Implemented Architecture We implemented the chosen MGD algorithm in both SystemC and VHDL hardware description languages. The hardware was implemented as a Galileo/GPS tracking structure with processes of carrier wipe-off, code tracking correlation, and result integration. The architecture of the implemented hardware delay tracking channel is illustrated in Figure 14 . The number of correlators is related to the algorithm used. For the chosen MGD structure with 𝑁 𝑔 = 3 , seven correlators are needed to form three correlator pairs and the prompt correlator. Figure 14: Implemented hardware tracking architecture with seven correlators. The implemented tracking architecture contains the following functional units: numerically controlled oscillators (NCOs) are used to create the desired frequencies inside the system for the replica code and carrier generation. The code generator is used to generate the replica PRN code for tracking. The carrier NCO outputs sine and cosine waves, which are used to strip the intermediate frequency (IF) carrier from the incoming signal. The sine and cosine multiplications make also the division between in-phase and quadrature phase channels. Seven correlators in both channels are used to correlate the incoming signal with the delayed versions of locally generated code. The amount of delay between the code generation outputs defines the spacings ( Δ 1 , Δ 2 , and Δ 3 ) between the correlators. Discriminator function is computed from the accumulated (integrated) correlator outputs. Since we decided to implement both uniform and decreasing spacing algorithms, two versions of the delay line in the code generator output was constructed. The main difference between these delay lines is illustrated in Figure 15 . The uniform delay spacing is created simply by feeding the reference code chip value from the code generator through a delay shift register, where all delays are equal (e.g., for Δ 1 = 0 . 2 5 chips, we have: 𝑍 − 1 = 0 . 1 2 5 chips). The decreasing delay spacing implementation needs additional registers between the very-very-early (VVE) and very-very-late (VVL) outputs to align the delays correctly (e.g., for Δ 1 = 0 . 2 5 chips, we have: 𝑍 − 1 = 0 . 0 3 1 2 5 chips, 𝑍 − 2 = 2 𝑍 − 1 = 0 . 0 6 2 5 chips, and 𝑍 − 4 = 4 𝑍 − 1 = 0 . 1 2 5 chips). One may notice that the decreasing delay spaced register implementation needs much smaller uniform delay 𝑍 − 1 . The relationship of smallest uniform delay 𝑍 − 1 in cases of uniform and decreasing delay spacings is 𝑍 − 1 u n i f o r m = 2 𝑁 𝑔 − 1 𝑍 − 1 d e c r e a s i n g . ( 1 6 ) Figure 15: Implemented delay registers: (a) uniform delay spacing, (b) decreasing delay spacing. Ref code is reference code chip value from code generator, VVE, VE, E are early, P is prompt, and L, VL, VVL late outputs of the delay register. The relative correlator spacings ( Δ 1 , Δ 2 , Δ 3 ) are illustrated on top. 𝑍 − 1 is the smallest uniform delay. 5.2. Systemc Verification of the Architecture We started the prototyping task by creating a high-level SystemC model of the hardware tracking channel. SystemC is a C++ library extension which can be used, for example, to cycle accurate hardware architecture modeling [ 36 ]. The similarity of the syntax of the hardware description language with C++ allowed fast prototype generation. Another benefit of using SystemC is that it contains the simulator itself, thus a stand-alone executable can be created for the simulations. The developed model was based on the one published previously in [ 37 ]. In [ 37 ], the SystemC hardware description language was used to model an inter-operative GPS/Galileo code correlator channel. For the MGD tracking algorithm testing, a carrier wipe-off process was included to this newer version of model. We developed a Matlab code to represent the software part of the proposed MGD tracking algorithms. Matlab was also used for generation of the input signals for the test simulations. The division of resources between SystemC model and Matlab software environment is illustrated in Figure 16 . The implemented SystemC model contains the same functional blocks as are illustrated in Figure 14 and, together with the surrounding Matlab environment, principally the same functionality as in Figure 3 . Figure 16: Block diagram of the implemented high-level SystemC hardware model inside the Matlab software. We used this SystemC model to see how the MEE curves of the proposed MGD algorithms behave when the hardware model is used. HRC and NEML algorithms were implemented for reference purposes. At first stage of MEE testing, we noticed that the envelopes ( p o w 𝑛 𝑐 = 1 ) generated with the SystemC model did have a constant negative offset. This can be seen clearly in Figure 17 , where the blue-squared curve illustrating the SystemC hardware-based MEE of NEML ( Δ 1 = 0 . 1 chips) has a negative offset when comparing to the black-star, plain Matlab based, and reference curve. On the other hand, the hardware model's MEE shares the same shape with the ideal reference one. Figure 17: Difference between the hardware model and Matlab-based MEE curves of NEML discriminator ( Δ 1 = 0 . 1 ). The black line presents the behavior of reference Matlab simulation, and the blue curve illustrates the behavior of the SystemC model. The reason for this behavior was found to be the imperfect frequency generation inside the hardware tracking channel. When both code generating and sampling frequency are generated with the NCO, there is a possibility to a sample slip if the NCO's frequency resolution is too low. With no noise condition (as MEEs are generated), this has an effect on the shape of ideal autocorrelation function curve, making it not to have identical sides. We improved the output accuracy of NCOs by increasing the accumulation register size from 24 to 32 bits. This removed the offset from the discriminator output as can be seen from Figure 18 , where red-diamond curve presents the MEE result with the new NCO size of 32 bits and blue-squared with NCO size of 24 bits. Figure 18: Effect of the NCO register length to the MEE curves of NEML discriminator ( Δ 1 = 0 . 1 chips) created by the SystemC model. The blue-squared curve presents the case when NCO register size was 24 bits; the red-diamond line is for the case of 32 bits. After the issue of the NCO size was dealt with, we made a conclusion that the proposed MGD algorithms are implementable, and the implemented hardware architecture is solid for this purpose. An example curve for the uniformly spaced ( Δ 1 = 0 . 1 , Δ 2 = 0 . 2 , Δ 3 = 0 . 3 chips) MGD structure ( 𝑁 𝑔 = 3 , p o w 𝑛 𝑐 = 1 ) is illustrated in Figure 19 . This figure shows how the shape of the hardware-based multipath envelope is similar to the one generated purely in Matlab in Figure 5 . Figures 19 and 5 also show the difference in envelope area when alternating between p o w 𝑛 𝑐 = 1 and p o w 𝑛 𝑐 = 2 . Figure 19: Example of the SystemC hardware-based MEE of the MGD ( 𝑁 𝑔 = 3 , p o w 𝑛 𝑐 = 1 , Δ 1 = 0 . 1 chips, uniform spacing) with SinBOC(1,1) signal. 5.3. VHDL Implementation and Synthesis After the architecture of the hardware tracking channel and its functionality with the proposed MGD structure were verified with the SystemC hardware model, we build a VHDL model of the tracking channel. VHSIC hardware description language (VHDL) is a language designed and optimized for describing the behavior of the digital systems, and it is one of the standard languages among the electronic engineers [ 16 ]. Since the VHDL needs a simulator software for simulation, we used ModelSim software and tool command language (TCL) scripts to run the simulations for MEE generation. The VHDL hardware-based MEE curve of the proposed MGD with both uniform ( 𝑎 = [ 1 , − 0 . 7 , − 0 . 2 ] ) and decreasing ( 𝑎 = [ 1 , − 0 . 9 , 0 . 2 ] ) spacing implementations are illustrated in Figure 20 . The blue-squared curve presents the uniform spaced MGD and the red-circled the decreasing spaced MGD, for both curves the common parameters were 𝑁 𝑔 = 3 , p o w 𝑛 𝑐 = 1 , and Δ 1 = 0 . 2 5 chips. From the figure, we can see that the MEE curves of the hardware implemented MGDs are active in the limits set by the theoretical ones, illustrated in Figure 6 . Figure 20: Example of VHDL hardware-based MEEs. MGD with uniform spacing ( 𝑎 = [ 1 , − 0 . 7 , − 0 . 2 ] ) is illustrated in blue-squared curve and MGD with decreasing spacing is illustrated ( 𝑎 = [ 1 , − 0 . 9 , 0 . 2 ] ) in red-circled. ( 𝑁 𝑔 = 3 , p o w 𝑛 𝑐 = 1 , Δ 1 = 0 . 2 5 ). We used the synthesis results of the VHDL model to evaluate the implementation complexity of the proposed algorithms. The synthesis was done by using the Xilinx ISE software. We varied the number of correlators, since it is the characterizing quantity when choosing the MGD algorithm to be implemented ( 𝑁 𝑔 ). Our target device was the Xilinx Virtex II PRO field programmable gate array (FPGA). FPGAs are reprogrammable digital devices which can be used in tasks requiring a high processing speed, like tracking process [ 32 ]. The synthesis results are subjected to the target platform and, therefore, they can not be generalized. Because of this, we focused on the comparison between the complexity of uniform and decreasing delay spaced implementations, with a varying number of correlators. We synthesized only the delay register part of the hardware architecture since it is the only part that differs. The results are illustrated in Figure 21 and in Table 6 . These results indicate that the hardware complexity, measured as usage of target FPGA resources (equivalent logic gate count, logic slices, flip flops, and lookup tables), increases linearly with respect to amount of correlators ( 𝑁 𝑔 ) in uniform delay spaced implementations. In cases of decreasing delay spaced implementations,. the complexity increase is much faster. One must note that the left out part of the system adds a constant positive offset to the synthesis results. Table 6: Xilinx resource usage. Figure 21: Synthesis of the architecture to the target device: effect of the number of correlators. Another difference between the implementations of uniform and decreasing delay spacings is in the increase of the generated frequencies when using the decreasing one. The proposed decreasing spacing structure with 𝑁 𝑔 = 3 requires approximately four times higher frequency to be generated than uniformly spaced MGD structure with equivalent 𝑁 𝑔 . This is because the smallest common uniform delay factor with the uniform spacing of Δ 1 = 0 . 2 5 chips is Δ 1 / 2 = 0 . 1 2 5 , but for the proposed decreasing spacing structure of Δ 1 = 0 . 2 5 chips it is Δ 1 / 8 = 0 . 0 3 1 2 5 . This equals to the reference code delay register frequency increase from 8.184 MHz up to 32.736 MHz with Galileo E1 and GPS C/A signals, when their fundamental frequency is 1.023 MHz. Also the limitation caused by the RF front-end bandwidth is met much faster when using the decreasing spacing, compared with uniform spacing. 6. Conclusions In this paper, a comprehensive description of Multiple Gate Delay tracking structures for GNSS signals in multipath environments has been introduced, covering all the steps from theoretical derivation and choice of design parameters till the final stage of prototyping. We showed that the proposed structures are implementable and that they have a high flexibility. We also explained in detail the design steps that should be taken in order to derive easily new MGD structures according to the target constraints (e.g., desired number of gate pairs, sampling frequencies, available bandwidths, etc.). We have discussed as well some aspects not taken into account in previous research papers, such as the effect of the nonlinearity type on the system performance, the design of gate spacings in multiple gate structures, and the effect of realistic PRN code lengths on the multipath error envelope analysis. We compared the MGD structures with uniform and decreasing spacings in terms of complexity, and we showed that the slightly better performance of MGDs with decreasing spacings is counter-balanced by a higher complexity, especially when the number of gate pairs increases. We showed that the state-of-art delay trackers, such as narrow correlator and double-delta correlators, can be seen as particular cases of MGD structures. We saw that the best choices in terms of two-path error envelopes are the MGDs with decreasing gate spacings and envelope nonlinearity. However, we also showed that, when the number of channel path increases, various MGD structures start to have equal performance, and the performance gap between narrow correlator and MGD structures disappears. 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International Journal of Navigation and Observation – Hindawi Publishing Corporation

**Published: ** May 21, 2008

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