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Daniel Flath (2018)
Introduction to Number Theory
P. Sotiriadis, G. Weaver (2007)
A Diophantine Frequency Synthesizer for the Examination of High Spectral Purity2007 IEEE International Frequency Control Symposium Joint with the 21st European Frequency and Time Forum
S. Cheng, J. Jensen, R. Wallis, G. Weaver (2004)
Further enhancements to the analysis of spectral purity in the application of practical direct digital synthesisProceedings of the 2004 IEEE International Frequency Control Symposium and Exposition, 2004.
P. Sotiriadis (2006)
Diophantine frequency synthesisIEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control, 53
B. Efron, R. Tibshirani (1995)
An Introduction to the Bootstrap
W. Egan (1981)
Frequency synthesis by phase lock
P. Sotiriadis (2006)
Diophantine Frequency Synthesis A Number Theory Approach to Fine Frequency Synthesis2006 IEEE International Frequency Control Symposium and Exposition
Hindawi Publishing Corporation International Journal of Navigation and Observation Volume 2008, Article ID 416958, 7 pages doi:10.1155/2008/416958 Research Article Diophantine Frequency Synthesizer Design for Timekeeping Systems 1 2 Paul P. Sotiriadis and Gregory L. Weaver Electrical and Computer Engineering, Johns Hopkins University, Baltimore, MD 21218, USA Space Department, Johns Hopkins University, Applied Physics Laboratory, Laurel, MD 20723, USA Correspondence should be addressed to Paul P. Sotiriadis, pps@ieee.org Received 2 August 2007; Accepted 21 November 2007 Recommended by Demetrios Matsakis Diophantine Frequency Synthesis (DFS), a number-theoretic approach to the design of very high resolution frequency synthe- sizers, was introduced in 2006. Further work concerning the impact of controlling mixing products for high-spectral purity was addressed and reported at the 2007 European Frequency and Time Forum. The focus of this paper is on the implementation of nested DFS architectures targeting microphase-type applications for precision timekeeping systems. We have shown that DFS does not impart any extraordinary design constraints on spectral purity in comparison to commonly used high resolution frequency synthesis techniques such as DDS or fractional N . Here we describe a design approach for 10 MHz synthesizers with 1E-13 frac- tional resolution in consecutive steps ranging ±10 Hz. The synthesizers generate their output from a 10 MHz reference standard. Such synthesizers are essential to accomplishing precision frequency correction in timekeeping systems. Copyright © 2008 P. P. Sotiriadis and G. L. Weaver. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. 1. INTRODUCTION nificantly taxing system complexity or resources. DFS pro- vides high spectral purity, even in synthesizers with much less In timekeeping systems, a local frequency and/or phase must than 0.1 PPM resolution steps. In general, we make this claim be generated and maintained to a very high degree of accu- in comparison with other fine resolution frequency synthe- racy. For example, the Time and Frequency Laboratory of sizer methods such as Direct Digital Synthesis (DDS) or the Johns Hopkins University Applied Physics Laboratory fractional-N modulators which are known to present a high degree of unwanted spurious signals into the output spec- maintains UTC (APL) within ±10 nanoseconds, based on monthly reports from the Bureau International des Poids et trum through the fundamental process that they impart on Mesures (BIPM). Modern timekeeping systems use phase- the input reference signal [3]. The use of DDS and fractional- frequency correction (steering) through auxiliary synthesiz- N synthesis design techniques has been widely adopted for ers to maintain the accuracy of their master clocks to UTC. timekeeping systems as high-frequency resolution (accuracy) The frequency step resolution of synthesizers for steering and fast acquisition (settling time) can be achieved with- timekeeping systems is typically 1 μHz or better. Designers out the complexity of traditional multiple loop synthesiz- of these very fine resolution synthesizers must carefully con- ers. However, DDS and fractional-N synthesizers both cause sider signal purity, resolution (accuracy to the global refer- phase perturbations in their basic operation schemes lead- ence), and complexity. Our paper describes the Diophantine ing to coherent spurious generation [3]. In the case of DDS, Frequency Synthesis (DFS) design approach for very fine fre- accuracy to a desired frequency necessarily compromises quency resolution synthesizers suitable for the maintenance the spectral purity of the output signal by the incidence of of autonomous clock holdover and microphase steering in truncation spurious attributable to the finite size of sin/cos laboratory timekeeping systems. lookup table and the DAC [4]. The novel DFS approach was introduced in 2006 [1, 2]. DFS uses only exactly periodic signals, without em- We have found that DFS alleviates the conventional trades ploying dithering, interpolation, pulse removal, or any other in performance for frequency synthesizer design without sig- approximately-periodic waveform that may corrupt the 2 International Journal of Navigation and Observation f 1 m 11 + m 1 1 × × N 3 in f Σ out f f in Σ out 9+ m m 2 + Figure 2: A simple two-PLL DFS scheme. Figure 1: A two-PLL DFS scheme. spectrum close to the carrier. DFS-based synthesizers present equals PLL’s phase-comparator frequency, that is, f /N and in 1 no discontinuity of the reference frequency phase, such as f /N , respectively. Therefore, to get smaller frequency steps in 2 DDS or fractional-N , and unlike these methods, DFS does (higher resolution) from a single PLL, a larger prescaler N notrequire anyspecial devicessuchashigh-resolutionDACs, and/or lower reference frequency f are required. This, nec- in accumulators, or sigma-delta modulators to control the spu- essarily results in a lower phase-comparator frequency f /N in i rious level of the output signal. implying slowed frequency lock acquisition (agility) and po- However, like traditional multiple loop PLL synthesizer tentially increased spurious signal levels closer to the carrier architectures, DFS does require mixing (or multiplication) signal of f [3]. out to achieve the output signal. This means that DFS synthe- DFS overcomes these problems as it allows simultane- sizers can suffer from unwanted spurious if attention to the ously for both high phase-comparator frequencies at the con- circuit design is not adequately respected. In our 2007 EFTF stituent PLLs and arbitrarily small frequency step at the out- paper, we described an approach for the design of VHF syn- put of the synthesizer. In the case of DFS scheme in Figure 1, thesizers with high-spectral purity of >100 dB spurious free the frequency step is dynamic range and showed that DFS presents no unique design-related constraints [5]. Rather, DFS design flexibility f in δf = (1) out provides an advantage to achieving this level of performance N N 1 2 in fine resolution frequency synthesis. which can be orders of magnitude smaller that f /N and in 1 f /N . This property of DFS is generalized in the case of k in 2 2. DFS—ELEMENTS OF THE THEORY PLLs. DFS is a number-theoretic approach to frequency synthesis. Throughout this paper, the prescalers (N ’s)ofthe PLLs It is based on mathematical properties of integer numbers are considered fixed in size. Moreover, it is assumed that and linear Diophantine equations [2] (by definition, a Dio- by design, the greatest common divisor of every pair of phantine equation is an algebraic equation whose solutions prescalers, (N , N ), is one , that is, the prescalers are pairwise i j are required to be integers [6]). prime integers; this is a requirement of the DFS methodology DFS results in high-level architectures using two or more [2]. Integer-N PLLs. It distributes the desirable output-frequency Finally, it is convenient to replace the value of every feed- resolution among these constituent PLLs in such a man- back divider m by the sum m + m (e.g., as in Figure 2), i i i ner that the resultant output fractional-frequency resolution where m is a fixed positive integer and the variable part, is equal to the product of the constituent PLLs’ fractional- m , is restricted to take integer values within the range −N i i frequency resolutions. Consequently, this property of DFS to N . So the range of values of the feedback divider is allows for the output frequency resolution to be made (ar- m − N ,... , m + N . i i i i bitrarily) fine, that is, to have a very small frequency step, without using large prescalers or low phase-comparator fre- 2.2. Basic numerical example of a two-PLL DFS scheme quencies in the PLL. Consider the architecture of Figure 2 consisting of two PLLs driven by the same reference frequency f , whose output fre- 2.1. The abstract DFS concept in quencies are summed resulting in DFS considers a PLL as a multiplier of an input frequency f in by a rational number m /N , as shown in Figure 1. i i 11 + m 9+ m 1 2 f = + f . (2) out in In Figure 1, two PLLs (i.e., two multipliers by m /N and 1 1 3 2 m /N ) are driven by the same reference frequency f .Their 2 2 in output signals are mixed (and the mixer’s output is filtered Following DFS methodology [2], the prescalers, N = 3 - not shown) to produce the synthesizer’s output signal of and N = 2, are fixed and relatively prime by design (small frequency f which typically is f = f + f ,asitishere, integers were selected here for illustration purposes). out out 1 2 or f = f − f . Further discussion on mixing follows in Thefeedback dividers are11 + m and 9 + m with out 1 2 1 2 Section 3. −3 ≤ m ≤ 3and −2 ≤ m ≤ 2. So, the range of each PLL 1 2 As it is always the case with integer-N PLLs, the fre- feedback divider is twice the size of the corresponding prescaler. quency resolution (step) of the individual PLLs in Figure 1 These imply that frequency f cantakeany of sevenvalues 1 P. P. Sotiriadis and G. L. W eaver 3 f ∈{8/3, 9/3,... ,14/3} and frequency f can take any of Table 1: Frequencies of the DFS example in Figure 2. 1 2 five values f ∈{7/2, 8/2,... ,11/2}. 11 9 m m 1 2 Table 1 shows (some of ) the output frequencies f that out f = + f + + f out in in 3 2 3 2 can be generated by using the DFS algorithm in [2]topro- 11 9 m m 1 2 gram the values of m and m within their preassumed ranges 1 2 m m a f /f = + + + 1 2 out in 3 2 3 2 −3 ≤ m ≤ 3and −2 ≤ m ≤ 2, respectively. Every one of 1 2 the thirteen triplets (m , m , a)in Table 1 satisfies the linear 1 2 −3 0 −6 43/6 = 49/6+ −6/6 Diophantine equation −1 −1 −5 44/6 = 49/6+ −5/6 m m a 1 2 + = . (3) 3 2 6 −2 0 −4 45/6 = 49/6+ −4/6 This way we can synthesize all frequencies of the form 0 −1 −3 46/6 = 49/6+ −3/6 −1 0 −2 47/6 = 49/6+ −2/6 f = f + f (4) out in out 1 −1 −1 48/6 = 49/6+ −1/6 with the variable a taking the values −6,−5,... , 6 and the 0 0 0 49/6 = 49/6+ 0 central frequency f being out −1 1 1 50/6 = 49/6+ 1/6 11 9 49 f = + f = f . (5) in in out 1 0 2 51/6 = 49/6+ 2/6 3 2 6 0 1 3 52/6 = 49/6+ 3/6 Note: the phase comparator frequencies of the individ- ual PLLs are f /3and f /2 while the synthesizer’s frequency in in 2 0 4 53/6 = 49/6+ 4/6 resolution (step size) is f /6. in In general, a two-PLL DFS synthesizer results in output 1 1 5 54/6 = 49/6+ 5/6 frequency 3 0 6 55/6 = 49/6+ 6/6 m m a 1 2 f = + f + f,(6) out in in N N N N 1 2 1 2 where the variable a can take any of the consecutive values m + m 1 1 from −N N to N N . This leads, by inspection of (6), to the 1 2 1 2 fundamental property of DFS that the frequency step can be made much smaller than the phase-comparator frequencies the constituent PLLs, that is, m + m 2 2 f f f in in in , . (7) N N N N 1 2 1 2 in Σ out Expression (6) itself results from our ability to find a con- . . . . . . venient solution of the linear Diophantine Equation . . . m m a 1 2 + = . (8) N N N N 1 2 1 2 m + m k k Note that the relationship between m , m ,and a,gov- N 1 2 k erned by (8), is nontrivial and in some cases is not unique, in the sense that there may be more than one pair of integers Figure 3: Abstract high-level k-PLL DFS scheme. (m , m ) that solve (8) for a particular value of integer a. 1 2 Furthermore, it has been proven that if we have a solu- tion (m , m )of (8)for a = 1, then we can easily generate 1 2 solutions for every other value of a; therefore in a hardware It has been proven, in [2], that when the integer variables implementation, very few numbers have to be stored. A de- m , m ,... , m are allowed to take any values in the intervals 1 2 k tailed description of how to solve linear Diophantine Equa- −N ≤ m ≤ N ,−N ≤ m ≤ N ,... ,−N ≤ m ≤ N , 1 1 1 2 2 2 k k k tions efficiently is also available in [2]. respectively, then the following set of frequencies can be syn- thesized: 2.3. DFS synthesizers with k PLLs The general abstract high-level architecture of k-PLL DFS f = f + f,(9) out in out synthesizers is shown in Figure 3. N N ··· N 1 2 k 4 International Journal of Navigation and Observation the harmonic contents of the mixed signals, and of course f f ± f in in the type of the mixers. The key to low-output spurs in DFS synthesizers is the VCO mixing method since the mixers are the dominant spurs gen- Filter erating circuit elements. Phase Loop 3.2. Frequency offsetting detector filter The synthesizer architecture in Figure 4 is convenient for de- Figure 4: Frequency-offset loop. riving the sum or difference between a large f and a small in offset frequency f . When f/ f 1, the mixing of f with f ± f can be in in in performed without difficulty and the mixing spurs can be where a can take any of the values minimal, for example, [5]. Therefore frequency offsetting is a =−N N ··· N ,... , N N ··· N (10) 1 2 k 1 2 k an effective approach to achieving the frequency summations and/or subtractions needed to realize DFS with central out- and the central frequency f is put frequency close to f . out in The following subsections illustrate this approach for the m m m 1 2 k case of two- and three-PLL DFS schemes. In principle, the f = + +··· + f . (11) in out N N N 1 2 k structure of Figure 4 can be cascaded k times to create k-PLL DFS architectures. Therefore, the frequency resolution (step) achieved by k-PLL DFS architectures is 3.3. Two-PLL frequency-offset DFS architecture in δf = . (12) out N N ··· N 1 2 k Figure 5 shows how two DFS-determined PLLs can be cas- caded using an offset synthesizer structure to form a DFS The central frequency f can be adjusted with resolu- out architecture, where the variable f canbeadjustedinvery out tion δf as well. The mathematical details, theorems, and out small-frequency steps from the reference f . in their proofs of the general k-PLL DFS architectures can be Based on the DFS theory [2], the two PLL output fre- found in [2]. quencies f , f (we can consider divider R as part of the 1 2 PLLs) are determined by the common dividers Q, R, the 3. FREQUENCY-OFFSET DFS two relatively prime integers N , N , and the feedback di- 1 2 ARCHITECTURES FOR VERY HIGH viders pN + m and pN + m which are partitioned into 1 1 2 2 FRACTIONAL-FREQUENCY RESOLUTION the fixed, pN , pN , and the variable, m , m , parts. The val- 1 2 1 2 ues of m , m program the value of parameter a in expression 1 2 Synthesizers with very high fractional-frequency resolution (6). The fixed integers pN and pN partially define the cen- 1 2 like microphase steppers, advanced signal generators, certain tral frequencies f , f of the PLLs. In this application, we 1 2 instrumentation equipment, atomic-clock synthesizers, and so forth, often have performance specifications that challenge also like to have f = f which implies that f = f when out in 1 2 existing technology solutions especially under cost, power, m = m = 0. 1 2 Variables m and m are allowed to take any value size, and complexity constraints. DFS offers a new alternative 1 2 to DDS and fractional-N PLLs in the design of such systems. within their ranges −N ,... , N and −N ,... , N ,respec- 1 1 2 2 tively. This results in output-frequency resolution equal to For this kind of applications, most appropriate DFS ar- δf = f /(QRN N ) and output-frequency range (equal to chitecture has been proven to be the one based on frequency out in 1 2 offsetting [3]. Since frequency offsetting requires mixing, a or greater than) Δ f =± f /(QR). (Note the product of N out in 1 and N in the denominator, in contrast to Q that is accounted few comments are in order without any intention to cover the topic of mixing. for on its first power.) The factor Q in the denominators determines the pul- lability ranges of the VCOs in the PLLs. Specifically, given 3.1. Frequency mixing the ranges of m and m , the VCO’s fractional pullability is 1 2 Mixing of two periodic signals at frequencies f and f is de- PL =± (100/Q) %. The role of p in the numerators 1 2 PLL 1,2 noted by ⊗,see Figure 4, and the outcome is typically chosen is to adjust for the central output frequencies of the PLLs to be either f + f or f − f . by counterbalancing Q. The phase-comparator frequencies 1 2 1 2 Mixing of three or more signals has a similar interpre- of the PLLs are f = f /(QN ), i = 1, 2. PC PLL i in i tation, note however that the order of performing the mix- Finally, R is a large divider necessary to generate the rela- ing of the signals may be important for getting a spectrally tively small frequencies f , f from the output frequencies of 1 2 pure output signal. In general, minimization of mixing spurs the PLLs. Divider R also contributes to the output resolution involves the choice of the central frequencies of f and f , of the synthesizer and the spectral purity of signals entering 1 2 their frequency ranges, the choice of the sum or difference, the frequency-offset blocks. P. P. Sotiriadis and G. L. W eaver 5 f + f Frequency in 1 Frequency f = f + f − f f out in 1 2 in offset + offset − PLL in pN + m Range: Δ f =± 1 1 out × ÷R 1 QR QN in Step: δf = PLL out QRN N 1 2 pN + m 2 2 × ÷R QN m : −N ,... , N 1 1 1 m : −N ,... , N 2 2 2 a : −N N ,... ,+N N 1 2 1 2 1 m m a 1 2 f = f + − f f + f out in in in in QR N N QRN N 1 2 1 2 Figure 5: Two-PLL frequency-offset DFS scheme. ∼ p δf out 10 μHz Q == 10 f f PLL = PLL = 10 MHz 1 2 Δ f out = ±10 Hz f f ∼ R = 100000 PC PLL PC PLL 1kHz 1= 2 −→ ⇒ f = 10 MHz in N = 1000 PL PL ±10% 1 PLL== PLL 1 2 out = 10 MHz N = 1017 f f 2 == 100 Hz 1 2 Figure 6: Numerical example of the two-PLL frequency-offset DFS scheme in Figure 5. With a microphase stepper application in mind, Figure 6 because of the odd number of PLLs, centering f with re- out shows a choice of values for N , N , R, Q,and p, and the spect to the input reference f requires further design con- 1 2 in corresponding characteristics and performance of the syn- sideration. thesizer they result in. A resolution of 10 μHz is probably the Specifically, it is desirable that m = m = m = 0implies 1 2 3 best that the two-PLL scheme with 10 MHz input frequency f = f . To achieve this, we add f and f to f and subtract out in 1 2 in could give. Note that although the 100 Hz frequency offset is f . Moreover, we introduce factors of 2 in PLL 3 and in the R- not uncommon in these types of systems, a higher frequency dividers of PLLs 1 and 2. These result in 2 f = 2 f = f = 1 2 3 would be helpful. The pullability range of ±10% is achievable pf /(QR)and equalrangesof f , f ,and f .However,the in 1 2 3 by tunable LC oscillators, and because of the large divider R, pullability range of PLL 3 is the half of that of PLLs 1 and 2. the phase noise of the oscillators is not a critical issue. The expression for f is shown in Figure 7. out As described in Figure 6, the magnitude of R was made Integers N , N ,and N are chosen to be pairwise prime 1 2 3 large compared to Q, N ,and N to achieve the desired 1 2 and the variables m , m ,and m take values within their 1 2 3 frequency-step resolution of ±10 μHz while keeping the PLL ranges −N ,... , N , −N ,... , N ,and −N ,... , N ,respec- 1 1 2 2 3 3 phase-comparator frequencies relatively large and easy to fil- tively. The resulting output frequency resolution is δf = out ter. This choice was not directed through any fundamental f /(2QRN N N ) and the output frequency range is (equal in 1 2 3 constraint in the DFS method, but was made from our de- to or greater than) Δ f =± f /(2QR). out in sign emphasis on high-spectral purity over acquisition speed Again, with a microphase stepper application in in a simple, practical circuit implementation. In the follow- mind, Figure 8 shows a choice of numerical values for ing subsection, we see how adding one more PLL allows for N , N , N , R, Q,and p, as well as the corresponding charac- more choices of the parameters and, in principle, better over- 1 2 3 teristics of the resulting synthesizer. Output frequency res- all performance. olution of 1 μHz and output range of about ±16 Hz are achieved. The frequency offset has been raised to 500 Hz for 3.4. Three-PLL frequency-offset DFS architecture PLLs 1, 2 and to 1000 Hz for PLL 3, and the pullability ranges A three-PLL frequency-offset DFS architecture is shown in have dropped to about ±3% and ±1.6%, respectively. There- Figure 7. Its principles of operation are very similar to those fore, as expected, the three-PLL case provides much more of the two-PLL one in Figure 5. The major difference is that flexibility in the design and much better characteristics. 6 International Journal of Navigation and Observation f + f f + f + f Frequency in 1 Frequency in 1 2 Frequency in f out offset + offset + offset − PLL pN + m 1 1 × ÷2R f QN PLL pN + m 2 2 × ÷2R QN PLL 2pN + m 3 3 × ÷R 2QN f f in in f = f + f + f − f Range: Δ f =± Step: δf = out in 1 2 3 out out 2QR 2QRN N N 1 2 3 m : −N ,... , N 1 1 1 m : −N ,... , N 2 2 2 m : −N ,... , N 3 3 3 a : −N N N ,... ,+N N N 1 2 3 1 2 3 1 m m m a 1 2 3 f = f + + − f = f + f out in in in in 2QR N N N 2QRN N N 1 2 3 1 2 3 Figure 7: Three-PLL frequency-offset DFS scheme. Q == 31 δf ∼ f f f out 1 μHz = PLL == PLL PLL = 10 MHz 1 2 3 R = 10000 Δ f ∼ out ±16 Hz f f f = PC PLL== PC PLL PC PLL 1kHz 1 2 3 = N = 319 −→ f = 10 MHz PL = PL =±3%, PL =±1.6% in PLL PLL PLL N = 317 1 2 3 N = 158 out = 10 MHz 3 f = f = 500 Hz, f = 1kHz 1 2 3 Figure 8: Numerical example of the three-PLL frequency-offset DFS scheme in Figure 7. 4. SUMMARY while the phase-comparator frequencies of the constituent PLLs are In summary, the general structure of DFS architectures pro- f f f vides the following desirable properties: the ability to achieve in in in , ,... , . (16) a predetermined center frequency N N N 1 2 k The application of DFS permits high flexibility on the m m m 1 2 k f = + +··· + f (13) in out relationship of the fixed-frequency reference to output fre- N N N 1 2 k quency (9) with wide-frequency range (14). Based on (15), we have shown the design of very fine frequency resolution with frequency range using two- and three-PLL nested DFS frequency-offset loops. In the case of the three-loop system described in Figure 7, f − f to f + f (14) in in out out a fractional frequency synthesizer capable of 1E-13 has been numerically demonstrated. The method of cascading nested and frequency step (resolution) of frequency-offset DFS architectures to higher orders would ultimately result in frequency steering resolution approach- in ing 1E-15, consistent with the needs of most precision time- δf = , (15) out N N ··· N 1 2 k keeping laboratories contributing to UTC. P. P. Sotiriadis and G. L. W eaver 7 ACKNOWLEDGMENTS The authors would like to express their appreciation to Dr. Demetrios Matsakis, Mr. Warren Walls, and Mr. Andradige Silva for their help on the Diophantine project. REFERENCES [1] P. P. Sotiriadis, “Diophantine frequency synthesis a number the- ory approach to fine frequency synthesis,” in Proceedings of IEEE International Frequency Control Symposium and Exposition,pp. 48–53, Miami, Fla, USA, June 2006. [2] P. P. Sotiriadis, “Diophantine frequency synthesis,” IEEE Trans- actionsonUltrasonics,Ferroelectrics, andFrequency Control, vol. 53, no. 11, pp. 1988–1998, 2006. [3] W.F.Egan, Frequency Synthesis by Phase Lock, John Wiley & Sons, New York, NY, USA, 2nd edition, 1999. [4] S. Cheng, J. R. Jensen, R. E. Wallis, and G. L. Weaver, “Further enhancements to the analysis of spectral purity in the applica- tion of practical direct digital synthesis,” in Proceedings of IEEE International Frequency Control Symposium and Exposition,pp. 462–470, Montreal, Canada, August 2004. [5] P. P. Sotiriadis and G. L. Weaver, “A diophantine frequency syn- thesizer for the examination of high spectral purity,” in Proceed- ings of IEEE International Frequency Control Symposium Jointly with the 21st European Frequency and Time Forum, pp. 1092– 1098, Geneva, Switzerland, May-June 2007. [6] D. E. Flath, Introduction to Number Theory,JohnWiley &Sons, New York, NY, USA, 1989. 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International Journal of Navigation and Observation – Hindawi Publishing Corporation
Published: Mar 18, 2008
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